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| author | Javed Absar <javed.absar@arm.com> | 2016-10-07 13:41:55 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2016-10-07 13:41:55 +0000 |
| commit | 9797989ca745518577a0fdef684cbdb642ea4df0 (patch) | |
| tree | 55327f8bafde52c9c222abe3e714c6e3fb2b062a /llvm | |
| parent | 04864f45b2f24e1268640cbde9203a7f769b6a79 (diff) | |
| download | bcm5719-llvm-9797989ca745518577a0fdef684cbdb642ea4df0.tar.gz bcm5719-llvm-9797989ca745518577a0fdef684cbdb642ea4df0.zip | |
[ARM]: add missing switch case for cortex-r52
Adds a missing switch case for handling cortex-r52
in init-subtarget-features.
llvm-svn: 283551
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index a90b4950288..f39e792025e 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -244,6 +244,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case CortexR7: case CortexM3: case ExynosM1: + case CortexR52: break; case Krait: PreISelOperandLatencyAdjustment = 1; |
