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authorChris Lattner <sabre@nondot.org>2005-08-26 21:49:18 +0000
committerChris Lattner <sabre@nondot.org>2005-08-26 21:49:18 +0000
commit97345405a6d9dbe8fabe6ed91d7233c06f627ad2 (patch)
treef1df1b2bd60301f67b882cc18994251a136d8e6d /llvm
parent4a5ebe94ba11976262772ef9a394f80c07610343 (diff)
downloadbcm5719-llvm-97345405a6d9dbe8fabe6ed91d7233c06f627ad2.tar.gz
bcm5719-llvm-97345405a6d9dbe8fabe6ed91d7233c06f627ad2.zip
Minor cleanups:
* avoid calling getClass() multiple times (it is relatively expensive) * Allow -disable-fp-elim to turn of frame pointer elimination. llvm-svn: 23104
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp15
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
index 478af930f92..282f1e45676 100644
--- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
@@ -81,11 +81,12 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
static const unsigned Opcode[] = {
PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
};
- unsigned OC = Opcode[getIdx(getClass(SrcReg))];
+ const TargetRegisterClass *RegClass = getClass(SrcReg);
+ unsigned OC = Opcode[getIdx(RegClass)];
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
- } else if (PPC32::CRRCRegisterClass == getClass(SrcReg)) {
+ } else if (RegClass == PPC32::CRRCRegisterClass) {
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
} else {
@@ -96,15 +97,16 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
void
PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx) const{
+ unsigned DestReg, int FrameIdx) const {
static const unsigned Opcode[] = {
PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
};
- unsigned OC = Opcode[getIdx(getClass(DestReg))];
+ const TargetRegisterClass *RegClass = getClass(SrcReg);
+ unsigned OC = Opcode[getIdx(RegClass)];
if (DestReg == PPC::LR) {
addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
- } else if (PPC32::CRRCRegisterClass == getClass(DestReg)) {
+ } else if (RegClass == PPC32::CRRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
} else {
@@ -139,8 +141,7 @@ void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
// if frame pointer elimination is disabled.
//
static bool hasFP(MachineFunction &MF) {
- MachineFrameInfo *MFI = MF.getFrameInfo();
- return MFI->hasVarSizedObjects();
+ return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
void PPC32RegisterInfo::
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