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authorCraig Topper <craig.topper@intel.com>2017-09-04 01:13:34 +0000
committerCraig Topper <craig.topper@intel.com>2017-09-04 01:13:34 +0000
commit959fc08f3a22cc5c42fcbda40f52c9e8e93a193d (patch)
treeabcef7136f2c765315da8c4c904263d366873bdb /llvm
parentbc13af84f2f429f4f7ae897dbee838f7064094f3 (diff)
downloadbcm5719-llvm-959fc08f3a22cc5c42fcbda40f52c9e8e93a193d.tar.gz
bcm5719-llvm-959fc08f3a22cc5c42fcbda40f52c9e8e93a193d.zip
[X86] Remove some unnecessary curly braces and blank line. NFC
llvm-svn: 312461
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp14
1 files changed, 5 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 58ea9e0ffd9..f7fe3e8add4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35732,28 +35732,24 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG,
}
// If lower/upper loads are the same and the only users of the load, then
// lower to a VBROADCASTF128/VBROADCASTI128/etc.
- if (auto *Ld = dyn_cast<LoadSDNode>(peekThroughOneUseBitcasts(SubVec2))) {
+ if (auto *Ld = dyn_cast<LoadSDNode>(peekThroughOneUseBitcasts(SubVec2)))
if (SubVec2 == SubVec && ISD::isNormalLoad(Ld) &&
- SDNode::areOnlyUsersOf({N, Vec.getNode()}, SubVec2.getNode())) {
+ SDNode::areOnlyUsersOf({N, Vec.getNode()}, SubVec2.getNode()))
return DAG.getNode(X86ISD::SUBV_BROADCAST, dl, OpVT, SubVec);
- }
- }
+
// If this is subv_broadcast insert into both halves, use a larger
// subv_broadcast.
- if (SubVec.getOpcode() == X86ISD::SUBV_BROADCAST && SubVec == SubVec2) {
+ if (SubVec.getOpcode() == X86ISD::SUBV_BROADCAST && SubVec == SubVec2)
return DAG.getNode(X86ISD::SUBV_BROADCAST, dl, OpVT,
SubVec.getOperand(0));
- }
// If we're inserting all zeros into the upper half, change this to
// an insert into an all zeros vector. We will match this to a move
// with implicit upper bit zeroing during isel.
- if (ISD::isBuildVectorAllZeros(SubVec.getNode())) {
+ if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
getZeroVector(OpVT, Subtarget, DAG, dl), SubVec2,
Vec.getOperand(2));
-
- }
}
}
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