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authorRichard Osborne <richard@xmos.com>2009-08-18 17:58:17 +0000
committerRichard Osborne <richard@xmos.com>2009-08-18 17:58:17 +0000
commit934d61648b61a9775642b8db9ed42f0e92a28b57 (patch)
treef78834bf1ef1d97d48de46587ecf881138b31eef /llvm
parentd7f34337895312465d3e5b98fe98d6cc0ef83ddd (diff)
downloadbcm5719-llvm-934d61648b61a9775642b8db9ed42f0e92a28b57.tar.gz
bcm5719-llvm-934d61648b61a9775642b8db9ed42f0e92a28b57.zip
Put data with relocations in the same sections as data without relocations.
llvm-svn: 79351
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp8
-rw-r--r--llvm/test/CodeGen/XCore/globals.ll56
2 files changed, 63 insertions, 1 deletions
diff --git a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
index 767611218a9..91cb11533df 100644
--- a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp
@@ -51,5 +51,11 @@ void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){
MCSectionXCore::Create(".cp.rodata", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC |
MCSectionXCore::SHF_CP_SECTION,
- SectionKind::getReadOnly(), false, getContext());
+ SectionKind::getReadOnlyWithRel(), false,
+ getContext());
+
+ // Dynamic linking is not supported. Data with relocations is placed in the
+ // same section as data without relocations.
+ DataRelSection = DataRelLocalSection = DataSection;
+ DataRelROSection = DataRelROLocalSection = ReadOnlySection;
}
diff --git a/llvm/test/CodeGen/XCore/globals.ll b/llvm/test/CodeGen/XCore/globals.ll
index c3d5f52e68c..8cb2ef36694 100644
--- a/llvm/test/CodeGen/XCore/globals.ll
+++ b/llvm/test/CodeGen/XCore/globals.ll
@@ -22,6 +22,43 @@ entry:
ret i32* @G3
}
+define i32 **@addr_G4() {
+entry:
+; CHECK: addr_G4:
+; CHECK: ldaw r0, dp[G4]
+ ret i32** @G4
+}
+
+define i32 **@addr_G5() {
+entry:
+; CHECK: addr_G5:
+; CHECK: ldaw r11, cp[G5]
+; CHECK: mov r0, r11
+ ret i32** @G5
+}
+
+define i32 **@addr_G6() {
+entry:
+; CHECK: addr_G6:
+; CHECK: ldaw r0, dp[G6]
+ ret i32** @G6
+}
+
+define i32 **@addr_G7() {
+entry:
+; CHECK: addr_G7:
+; CHECK: ldaw r11, cp[G7]
+; CHECK: mov r0, r11
+ ret i32** @G7
+}
+
+define i32 *@addr_G8() {
+entry:
+; CHECK: addr_G8:
+; CHECK: ldaw r0, dp[G8]
+ ret i32* @G8
+}
+
@G1 = global i32 4712
; CHECK: .section .dp.data,"awd",@progbits
; CHECK: G1:
@@ -34,3 +71,22 @@ entry:
; CHECK: .section .cp.rodata,"ac",@progbits
; CHECK: G3:
+@G4 = global i32* @G1
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G4:
+
+@G5 = constant i32* @G1
+; CHECK: .section .cp.rodata,"ac",@progbits
+; CHECK: G5:
+
+@G6 = global i32* @G8
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G6:
+
+@G7 = constant i32* @G8
+; CHECK: .section .cp.rodata,"ac",@progbits
+; CHECK: G7:
+
+@G8 = internal global i32 9312
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G8:
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