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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-10-11 21:03:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-10-11 21:03:36 +0000 |
| commit | 8fb373891fa4b4452f40e81c8581c8f262da610c (patch) | |
| tree | a5eb34d7c537ae4d9783bc944bdb8c22467d073b /llvm | |
| parent | f5d9d348f7b362c09c0a14160c2c8a5517f717ea (diff) | |
| download | bcm5719-llvm-8fb373891fa4b4452f40e81c8581c8f262da610c.tar.gz bcm5719-llvm-8fb373891fa4b4452f40e81c8581c8f262da610c.zip | |
Fix typo
llvm-svn: 192499
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index c0db7f9c2b0..8294fbd71e6 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1195,7 +1195,7 @@ def LOAD_CONST : AMDGPUShaderInst < [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] >; -// SI Psuedo instructions. These are used by the CFG structurizer pass +// SI pseudo instructions. These are used by the CFG structurizer pass // and should be lowered to ISA instructions prior to codegen. let mayLoad = 1, mayStore = 1, hasSideEffects = 1, |
