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| author | Richard Smith <richard-llvm@metafoo.co.uk> | 2012-08-15 01:39:31 +0000 |
|---|---|---|
| committer | Richard Smith <richard-llvm@metafoo.co.uk> | 2012-08-15 01:39:31 +0000 |
| commit | 8f3447c032dc302da21e73b0c8e6afc1b6b5342f (patch) | |
| tree | 36d55d1aa10e3aedd747da28ad238690aa8b957a /llvm | |
| parent | f3bb0b2a9bbcf5347170f028a8a2d10b4c70eb04 (diff) | |
| download | bcm5719-llvm-8f3447c032dc302da21e73b0c8e6afc1b6b5342f.tar.gz bcm5719-llvm-8f3447c032dc302da21e73b0c8e6afc1b6b5342f.zip | |
Fix undefined behavior: don't perform array indexing through a potentially null
pointer.
llvm-svn: 161919
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 172402e20d6..f745b41c16f 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -681,10 +681,10 @@ void MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { const MachineInstr *MI = MO->getParent(); const MCInstrDesc &MCID = MI->getDesc(); - const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; // The first MCID.NumDefs operands must be explicit register defines if (MONum < MCID.getNumDefs()) { + const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; if (!MO->isReg()) report("Explicit definition must be a register", MO, MONum); else if (!MO->isDef() && !MCOI.isOptionalDef()) @@ -692,6 +692,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { else if (MO->isImplicit()) report("Explicit definition marked as implicit", MO, MONum); } else if (MONum < MCID.getNumOperands()) { + const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; // Don't check if it's the last operand in a variadic instruction. See, // e.g., LDM_RET in the arm back end. if (MO->isReg() && |
