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authorChad Rosier <mcrosier@codeaurora.org>2017-01-24 18:08:10 +0000
committerChad Rosier <mcrosier@codeaurora.org>2017-01-24 18:08:10 +0000
commit8e11fbd15d636510abd4e13b99af4418ff62a79b (patch)
treec50503f65502c0a0fd14ea779cdc77c2c6f5edbe /llvm
parent77dd30b5572ccccf00f49221a47f9ecf84c951ac (diff)
downloadbcm5719-llvm-8e11fbd15d636510abd4e13b99af4418ff62a79b.tar.gz
bcm5719-llvm-8e11fbd15d636510abd4e13b99af4418ff62a79b.zip
[AArch64] Fix typo. NFC.
llvm-svn: 292959
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/AArch64/AArch64.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 3cb7d0ecc85..cb6d8fc9668 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -296,11 +296,11 @@ def : ProcessorModel<"generic", NoSchedModel, [
FeaturePostRAScheduler
]>;
-// FIXME: Cortex-A35 is currently modelled as a Cortex-A53
+// FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
-// FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
+// FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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