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authorArtyom Skrobov <Artyom.Skrobov@arm.com>2017-04-21 07:35:21 +0000
committerArtyom Skrobov <Artyom.Skrobov@arm.com>2017-04-21 07:35:21 +0000
commit8d9643009f981435c4a6bd391f837c2680ec2d9a (patch)
tree61104d406b4199f12aad46cf713f86bc99d1bfd8 /llvm
parentc9a752c5b720ac82aebff830b78cc8257f051491 (diff)
downloadbcm5719-llvm-8d9643009f981435c4a6bd391f837c2680ec2d9a.tar.gz
bcm5719-llvm-8d9643009f981435c4a6bd391f837c2680ec2d9a.zip
[Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing `Uses = [CPSR]`
Summary: Thanks to Oliver Stannard for helping catch this. Reviewers: olista01, efriedma Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D31815 llvm-svn: 300951
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb.td3
-rw-r--r--llvm/test/CodeGen/Thumb/long.ll31
2 files changed, 33 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index f2f426e8670..8048c758e99 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -953,7 +953,7 @@ let isAdd = 1 in {
/// These opcodes will be converted to the real non-S opcodes by
/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
let hasPostISelHook = 1, Defs = [CPSR] in {
- let isCommutable = 1 in
+ let isCommutable = 1, Uses = [CPSR] in
def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
2, IIC_iALUr,
[(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
@@ -1292,6 +1292,7 @@ def tSUBrr : // A8.6.212
/// These opcodes will be converted to the real non-S opcodes by
/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
let hasPostISelHook = 1, Defs = [CPSR] in {
+ let Uses = [CPSR] in
def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
2, IIC_iALUr,
[(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,
diff --git a/llvm/test/CodeGen/Thumb/long.ll b/llvm/test/CodeGen/Thumb/long.ll
index c549bd425aa..13951ef4354 100644
--- a/llvm/test/CodeGen/Thumb/long.ll
+++ b/llvm/test/CodeGen/Thumb/long.ll
@@ -206,3 +206,34 @@ entry:
; CHECK: adds r0, r0, r2
; CHECK: sbcs r1, r3
}
+
+declare void @f13(i64 %x)
+
+define void @f14(i1 %x, i64 %y) #0 {
+; CHECK-LABEL: f14:
+entry:
+ %a = add i64 %y, 47
+ call void @f13(i64 %a)
+; CHECK: bl
+ br i1 %x, label %if.end, label %if.then
+
+if.then:
+ call void @f13(i64 %y)
+; CHECK: bl
+ br label %if.end
+
+if.end:
+ %b = add i64 %y, 45
+ call void @f13(i64 %b)
+; CHECK: adds
+; CHECK: adcs
+; CHECK: bl
+ %c = add i64 %y, 47
+ call void @f13(i64 %c)
+; CHECK: adds
+; CHECK-NEXT: adcs
+; CHECK: bl
+ ret void
+}
+
+attributes #0 = { optsize }
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