Sched itinerary fix: Avoid static initializers.

This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

llvm-svn: 158215

2 files changed, 14 insertions, 5 deletions

diff --git a/llvm/include/llvm/MC/MCInstrItineraries.h b/llvm/include/llvm/MC/MCInstrItineraries.h
index 62e19143482..05baddd918a 100644
--- a/llvm/include/llvm/MC/MCInstrItineraries.h
+++ b/llvm/include/llvm/MC/MCInstrItineraries.h
@@ -111,6 +111,7 @@ struct InstrItineraryProps {
   // IssueWidth is the maximum number of instructions that may be scheduled in
   // the same per-cycle group.
   unsigned IssueWidth;
+  static const unsigned DefaultIssueWidth = 1;
 
   // MinLatency is the minimum latency between a register write
   // followed by a data dependent read. This determines which
@@ -133,12 +134,14 @@ struct InstrItineraryProps {
   //      Optional InstrItinerary OperandCycles provides expected latency.
   //      TODO: can't yet specify both min and expected latency per operand.
   int MinLatency;
+  static const unsigned DefaultMinLatency = -1;
 
   // LoadLatency is the expected latency of load instructions.
   //
   // If MinLatency >= 0, this may be overriden for individual load opcodes by
   // InstrItinerary OperandCycles.
   unsigned LoadLatency;
+  static const unsigned DefaultLoadLatency = 4;
 
   // HighLatency is the expected latency of "very high latency" operations.
   // See TargetInstrInfo::isHighLatencyDef().
@@ -146,9 +149,16 @@ struct InstrItineraryProps {
   // likely to have some impact on scheduling heuristics.
   // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
   unsigned HighLatency;
-
-  InstrItineraryProps(): IssueWidth(1), MinLatency(-1), LoadLatency(4),
-                         HighLatency(10) {}
+  static const unsigned DefaultHighLatency = 10;
+
+  // Default's must be specified as static const literals so that tablegenerated
+  // target code can use it in static initializers. The defaults need to be
+  // initialized in this default ctor because some clients directly instantiate
+  // InstrItineraryData instead of using a generated itinerary.
+  InstrItineraryProps(): IssueWidth(DefaultMinLatency),
+                         MinLatency(DefaultMinLatency),
+                         LoadLatency(DefaultLoadLatency),
+                         HighLatency(DefaultHighLatency) {}
 
   InstrItineraryProps(unsigned iw, int ml, unsigned ll, unsigned hl):
     IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl) {}
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 764fc88c2e5..5911d9856f6 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -485,7 +485,7 @@ void SubtargetEmitter::EmitItineraryProp(raw_ostream &OS, const Record *R,
   if (V >= 0)
     OS << V << Separator << " // " << Name;
   else
-    OS << "DefaultItineraryProps." << Name << Separator;
+    OS << "InstrItineraryProps::Default" << Name << Separator;
   OS << '\n';
 }
 
@@ -496,7 +496,6 @@ void SubtargetEmitter::
 EmitProcessorData(raw_ostream &OS,
                   std::vector<Record*> &ItinClassList,
                   std::vector<std::vector<InstrItinerary> > &ProcList) {
-  OS << "static const llvm::InstrItineraryProps " << "DefaultItineraryProps;";
 
   // Get an iterator for processor itinerary stages
   std::vector<std::vector<InstrItinerary> >::iterator