[X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake

Sandy Bridge is also missing it, but it has other issues. See PR35590.

llvm-svn: 320292

4 files changed, 16 insertions, 16 deletions

diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 1492f9fd6f9..50d9452874d 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -3990,8 +3990,8 @@ def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[BWWriteResGroup191], (instregex "IN32ri")>;
-def: InstRW<[BWWriteResGroup191], (instregex "IN32rr")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)ri")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)rr")>;
 def: InstRW<[BWWriteResGroup191], (instregex "IN8ri")>;
 def: InstRW<[BWWriteResGroup191], (instregex "IN8rr")>;
 
@@ -4008,8 +4008,8 @@ def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPor
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[BWWriteResGroup194], (instregex "OUT32ir")>;
-def: InstRW<[BWWriteResGroup194], (instregex "OUT32rr")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)ir")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)rr")>;
 def: InstRW<[BWWriteResGroup194], (instregex "OUT8ir")>;
 def: InstRW<[BWWriteResGroup194], (instregex "OUT8rr")>;
 
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 5665470fd8d..d32d3796a46 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -4391,8 +4391,8 @@ def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[HWWriteResGroup170], (instregex "IN32ri")>;
-def: InstRW<[HWWriteResGroup170], (instregex "IN32rr")>;
+def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)ri")>;
+def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)rr")>;
 def: InstRW<[HWWriteResGroup170], (instregex "IN8ri")>;
 def: InstRW<[HWWriteResGroup170], (instregex "IN8rr")>;
 
@@ -4401,8 +4401,8 @@ def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPor
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[HWWriteResGroup171], (instregex "OUT32ir")>;
-def: InstRW<[HWWriteResGroup171], (instregex "OUT32rr")>;
+def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)ir")>;
+def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)rr")>;
 def: InstRW<[HWWriteResGroup171], (instregex "OUT8ir")>;
 def: InstRW<[HWWriteResGroup171], (instregex "OUT8rr")>;
 
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index ee10db31c07..cde59e89927 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -4099,8 +4099,8 @@ def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,S
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[SKLWriteResGroup209], (instregex "IN32ri")>;
-def: InstRW<[SKLWriteResGroup209], (instregex "IN32rr")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)ri")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)rr")>;
 def: InstRW<[SKLWriteResGroup209], (instregex "IN8ri")>;
 def: InstRW<[SKLWriteResGroup209], (instregex "IN8rr")>;
 
@@ -4109,8 +4109,8 @@ def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[SKLWriteResGroup210], (instregex "OUT32ir")>;
-def: InstRW<[SKLWriteResGroup210], (instregex "OUT32rr")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)ir")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)rr")>;
 def: InstRW<[SKLWriteResGroup210], (instregex "OUT8ir")>;
 def: InstRW<[SKLWriteResGroup210], (instregex "OUT8rr")>;
 
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index a86adbd7b7f..fe3dfd5879c 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -6801,8 +6801,8 @@ def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,S
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,3,4,10];
 }
-def: InstRW<[SKXWriteResGroup247], (instregex "IN32ri")>;
-def: InstRW<[SKXWriteResGroup247], (instregex "IN32rr")>;
+def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)ri")>;
+def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)rr")>;
 def: InstRW<[SKXWriteResGroup247], (instregex "IN8ri")>;
 def: InstRW<[SKXWriteResGroup247], (instregex "IN8rr")>;
 
@@ -6811,8 +6811,8 @@ def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,
   let NumMicroOps = 23;
   let ResourceCycles = [1,5,2,1,4,10];
 }
-def: InstRW<[SKXWriteResGroup248], (instregex "OUT32ir")>;
-def: InstRW<[SKXWriteResGroup248], (instregex "OUT32rr")>;
+def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)ir")>;
+def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)rr")>;
 def: InstRW<[SKXWriteResGroup248], (instregex "OUT8ir")>;
 def: InstRW<[SKXWriteResGroup248], (instregex "OUT8rr")>;