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| author | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-11-01 10:26:48 +0000 |
|---|---|---|
| committer | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-11-01 10:26:48 +0000 |
| commit | 8a89d3662a8ce311ff55eef68d9a3910d9bfeeef (patch) | |
| tree | 99fb25f815fbe3322ff13a899616dcb6efd54dc2 /llvm | |
| parent | d0a9d1499cf6c49fbb441660d37032eae694ee37 (diff) | |
| download | bcm5719-llvm-8a89d3662a8ce311ff55eef68d9a3910d9bfeeef.tar.gz bcm5719-llvm-8a89d3662a8ce311ff55eef68d9a3910d9bfeeef.zip | |
[AMDGPU] Expand vector mulhu/mulhs
Differential revision: https://reviews.llvm.org/D26077
llvm-svn: 285684
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/sdiv.ll | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/udiv.ll | 13 |
3 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index a7fd748e85d..a69d1afdea8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -359,6 +359,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP_TO_SINT, VT, Expand); setOperationAction(ISD::FP_TO_UINT, VT, Expand); setOperationAction(ISD::MUL, VT, Expand); + setOperationAction(ISD::MULHU, VT, Expand); + setOperationAction(ISD::MULHS, VT, Expand); setOperationAction(ISD::OR, VT, Expand); setOperationAction(ISD::SHL, VT, Expand); setOperationAction(ISD::SRA, VT, Expand); diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll index 29d893414c0..66caad4677b 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll @@ -156,3 +156,16 @@ define void @v_sdiv_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) { ; store i64 %result, i64 addrspace(1)* %out, align 8 ; ret void ; } + +; FUNC-LABEL: @scalarize_mulhs_4xi32 +; SI: v_mul_hi_i32 +; SI: v_mul_hi_i32 +; SI: v_mul_hi_i32 +; SI: v_mul_hi_i32 + +define void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { + %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 + %2 = sdiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668> + store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll index f72c22095e4..02383a97205 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv.ll @@ -145,3 +145,16 @@ define void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) { store i32 %result.ext, i32 addrspace(1)* %out ret void } + +; FUNC-LABEL: @scalarize_mulhu_4xi32 +; SI: v_mul_hi_u32 +; SI: v_mul_hi_u32 +; SI: v_mul_hi_u32 +; SI: v_mul_hi_u32 + +define void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { + %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 + %2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668> + store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 + ret void +} |
