Revert r150565 again. Appears to be a stage2 failure with dragonegg.

I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it.

llvm-svn: 150568

1 files changed, 8 insertions, 6 deletions

diff --git a/llvm/lib/CodeGen/Passes.cpp b/llvm/lib/CodeGen/Passes.cpp
index 8fb94162b28..ec1f2b4c3b2 100644
--- a/llvm/lib/CodeGen/Passes.cpp
+++ b/llvm/lib/CodeGen/Passes.cpp
@@ -582,8 +582,14 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
   //
   // FIXME: Re-enable coloring with register when it's capable of adding
   // kill markers.
-  if (addPass(StackSlotColoringID) != &NoPassID)
-    printAndVerify("After StackSlotColoring");
+  addPass(StackSlotColoringID);
+
+  // Run post-ra machine LICM to hoist reloads / remats.
+  //
+  // FIXME: can this move into MachineLateOptimization?
+  addPass(PostRAMachineLICMID);
+
+  printAndVerify("After StackSlotColoring and postra Machine LICM");
 }
 
 //===---------------------------------------------------------------------===//
@@ -592,10 +598,6 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
 
 /// Add passes that optimize machine instructions after register allocation.
 void TargetPassConfig::addMachineLateOptimization() {
-  // Run post-ra machine LICM to hoist reloads / remats.
-  if (addPass(PostRAMachineLICMID) != &NoPassID)
-    printAndVerify("After postra Machine LICM");
-
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (addPass(BranchFolderPassID) != &NoPassID)
     printNoVerify("After BranchFolding");