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author | Chris Lattner <sabre@nondot.org> | 2007-10-18 06:17:07 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2007-10-18 06:17:07 +0000 |
commit | 84f3461c49272ad53c7c62d822d42c6f70a2c8fb (patch) | |
tree | 60f877de436bffcd631df20ea1e322cc4620f3bf /llvm | |
parent | ca831a829d7a3ce67142378e653b12ae963bf8c1 (diff) | |
download | bcm5719-llvm-84f3461c49272ad53c7c62d822d42c6f70a2c8fb.tar.gz bcm5719-llvm-84f3461c49272ad53c7c62d822d42c6f70a2c8fb.zip |
legalizing the ret operation on f64 shouldn't introduce a new
i64 bit convert needlessly.
llvm-svn: 43116
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index a242c4d140c..15a84091688 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -670,10 +670,12 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { if (Op.getValueType() == MVT::f32) { Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); } else if (Op.getValueType() == MVT::f64) { - // Recursively legalize f64 -> i64. - Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op); - return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, - DAG.getConstant(0, MVT::i32)); + // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is + // available. + Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); + SDOperand Sign = DAG.getConstant(0, MVT::i32); + return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, + Op.getValue(1), Sign); } Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); if (DAG.getMachineFunction().liveout_empty()) |