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| author | Scott Michel <scottm@aero.org> | 2007-12-05 21:23:16 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2007-12-05 21:23:16 +0000 |
| commit | 83d54c9ee0b0839973109fe28a08943c8cd21a52 (patch) | |
| tree | f9400cb02f8d6273d64cfd1724684dc1ba4c4bc0 /llvm | |
| parent | abba5e218c930f15753fa305479b16d141ebd751 (diff) | |
| download | bcm5719-llvm-83d54c9ee0b0839973109fe28a08943c8cd21a52.tar.gz bcm5719-llvm-83d54c9ee0b0839973109fe28a08943c8cd21a52.zip | |
Minor updates:
- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list
llvm-svn: 44627
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/CREDITS.TXT | 4 | ||||
| -rw-r--r-- | llvm/autoconf/configure.ac | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUCallingConv.td | 3 |
3 files changed, 6 insertions, 4 deletions
diff --git a/llvm/CREDITS.TXT b/llvm/CREDITS.TXT index bf02b165ecd..c4e0bb7eff8 100644 --- a/llvm/CREDITS.TXT +++ b/llvm/CREDITS.TXT @@ -257,3 +257,7 @@ W: http://web.mac.com/bwendling/ D: Darwin exception handling D: MMX & SSSE3 instructions D: SPEC2006 support + +N: Scott Michel +E: scottm@aero.org +D: Added STI Cell SPU backend. diff --git a/llvm/autoconf/configure.ac b/llvm/autoconf/configure.ac index 9a183d4fcfe..979e3a89865 100644 --- a/llvm/autoconf/configure.ac +++ b/llvm/autoconf/configure.ac @@ -363,8 +363,7 @@ AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets], [Build specific host targets: all,host-only,{target-name} (default=all)]),, enableval=all) case "$enableval" in - # Note: Add "CellSPU" to all when fully functional. - all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips" ;; + all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU" ;; host-only) case "$llvm_cv_target_arch" in x86) TARGETS_TO_BUILD="X86" ;; diff --git a/llvm/lib/Target/CellSPU/SPUCallingConv.td b/llvm/lib/Target/CellSPU/SPUCallingConv.td index 93a4000b858..47f8f3ca614 100644 --- a/llvm/lib/Target/CellSPU/SPUCallingConv.td +++ b/llvm/lib/Target/CellSPU/SPUCallingConv.td @@ -48,7 +48,6 @@ def CC_SPU : CallingConv<[ // The first 12 Vector arguments are passed in altivec registers. CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>> - */ /* // Integer/FP values get stored in stack slots that are 8 bytes in size and // 8-byte aligned if there are no more registers to hold them. @@ -56,6 +55,6 @@ def CC_SPU : CallingConv<[ // Vectors get 16-byte stack slots that are 16-byte aligned. CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], - CCAssignToStack<16, 16>> + CCAssignToStack<16, 16>>*/ ]>; */ |
