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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-23 15:20:01 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-23 15:20:01 +0000 |
| commit | 82f364515c525bff550f741c52a2479581effc77 (patch) | |
| tree | 966670df547ad1ffef469e6f3654b591f404d25f /llvm | |
| parent | e36d77b7264ad838a619cc86fbf4c9b8cb42abed (diff) | |
| download | bcm5719-llvm-82f364515c525bff550f741c52a2479581effc77.tar.gz bcm5719-llvm-82f364515c525bff550f741c52a2479581effc77.zip | |
don't lie to the register allocator
llvm-svn: 20784
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index d25c36eb7fa..abf9934f56e 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1068,7 +1068,7 @@ unsigned ISel::SelectExpr(SDOperand N) { unsigned Tmp9 = MakeReg(MVT::f64); BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdxL).addReg(Alpha::F31); - BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdxR).addReg(Alpha::F31); + BuildMI(BB, Alpha::STQ, 3).addReg(Tmp2).addFrameIndex(FrameIdxR).addReg(Alpha::F31); BuildMI(BB, Alpha::LDT, 2, Tmp4).addFrameIndex(FrameIdxL).addReg(Alpha::F31); BuildMI(BB, Alpha::LDT, 2, Tmp5).addFrameIndex(FrameIdxR).addReg(Alpha::F31); BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Tmp4); @@ -1076,7 +1076,7 @@ unsigned ISel::SelectExpr(SDOperand N) { BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7); BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Tmp8); BuildMI(BB, Alpha::STT, 3).addReg(Tmp9).addFrameIndex(FrameIdxF).addReg(Alpha::F31); - BuildMI(BB, Alpha::LDQ, 3).addReg(Result).addFrameIndex(FrameIdxF).addReg(Alpha::F31); + BuildMI(BB, Alpha::LDQ, 2, Result).addFrameIndex(FrameIdxF).addReg(Alpha::F31); return Result; } |
