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| author | Amara Emerson <amara.emerson@arm.com> | 2014-08-15 14:29:57 +0000 |
|---|---|---|
| committer | Amara Emerson <amara.emerson@arm.com> | 2014-08-15 14:29:57 +0000 |
| commit | 82da7d07a1c3c21298c769beb74971facbf52f64 (patch) | |
| tree | 0aa26dc8984f0fe2cfec5222434d5b7f105fc91c /llvm | |
| parent | ed735d336049ea5c05aca2efb5eb5b9086732dd9 (diff) | |
| download | bcm5719-llvm-82da7d07a1c3c21298c769beb74971facbf52f64.tar.gz bcm5719-llvm-82da7d07a1c3c21298c769beb74971facbf52f64.zip | |
[AArch64] Narrow arguments passed in wrong position on the stack in
big-endian mode.
Patch by Asiri Rathnayake.
Differential Revision: http://reviews.llvm.org/D4922
llvm-svn: 215716
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll | 24 |
2 files changed, 26 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 53ac50ec802..be9d8d67afd 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1779,7 +1779,7 @@ SDValue AArch64TargetLowering::LowerFormalArguments( } else { // VA.isRegLoc() assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem"); unsigned ArgOffset = VA.getLocMemOffset(); - unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; + unsigned ArgSize = VA.getValVT().getSizeInBits() / 8; uint32_t BEAlign = 0; if (ArgSize < 8 && !Subtarget->isLittleEndian()) @@ -2321,7 +2321,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, // common case. It should also work for fundamental types too. uint32_t BEAlign = 0; unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 - : VA.getLocVT().getSizeInBits(); + : VA.getValVT().getSizeInBits(); OpSize = (OpSize + 7) / 8; if (!Subtarget->isLittleEndian() && !Flags.isByVal()) { if (OpSize < 8) diff --git a/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll b/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll new file mode 100644 index 00000000000..77e2b0f717b --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-aapcs-be.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple=aarch64_be-none-eabi -fast-isel=false < %s | FileCheck %s +; RUN: llc -mtriple=aarch64_be-none-eabi -fast-isel=true < %s | FileCheck %s + +; Check narrow argument passing via stack - callee end +define i32 @test_narrow_args_callee(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, i8 %c, i16 %s) #0 { +entry: + %conv = zext i8 %c to i32 + %conv1 = sext i16 %s to i32 + %add = add nsw i32 %conv1, %conv +; CHECK-LABEL: test_narrow_args_callee: +; CHECK-DAG: ldrb w{{[0-9]}}, [sp, #7] +; CHECK-DAG: ldr{{s?}}h w{{[0-9]}}, [sp, #14] + ret i32 %add +} + +; Check narrow argument passing via stack - caller end +define i32 @test_narrow_args_caller() #0 { +entry: + %call = tail call i32 @test_narrow_args_callee(i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i8 8, i16 9) +; CHECK-LABEL: test_narrow_args_caller: +; CHECK-DAG: strh w{{[0-9]}}, [sp, #14] +; CHECK-DAG: strb w{{[0-9]}}, [sp, #7] + ret i32 %call +}
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