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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-05-10 02:09:29 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-05-10 02:09:29 +0000 |
| commit | 7fb3963498363f78b30d65e07014e9690a7b1059 (patch) | |
| tree | 6f61fc9eeb30b56dc2522d457ba87888727298d1 /llvm | |
| parent | a99c6ae47a72aa7ec836fd7569c17e189ebcda02 (diff) | |
| download | bcm5719-llvm-7fb3963498363f78b30d65e07014e9690a7b1059.tar.gz bcm5719-llvm-7fb3963498363f78b30d65e07014e9690a7b1059.zip | |
R600: Expand SRA for v4i32/v2i32
v2: Add v4i32 test
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181577
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/R600ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/sra.ll | 13 |
2 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index 6dec4d1dbe3..ac56ed86438 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -50,6 +50,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::SHL, MVT::v2i32, Expand); setOperationAction(ISD::SRL, MVT::v4i32, Expand); setOperationAction(ISD::SRL, MVT::v2i32, Expand); + setOperationAction(ISD::SRA, MVT::v4i32, Expand); + setOperationAction(ISD::SRA, MVT::v2i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand); setOperationAction(ISD::UDIV, MVT::v4i32, Expand); setOperationAction(ISD::UREM, MVT::v4i32, Expand); diff --git a/llvm/test/CodeGen/R600/sra.ll b/llvm/test/CodeGen/R600/sra.ll new file mode 100644 index 00000000000..972542d346f --- /dev/null +++ b/llvm/test/CodeGen/R600/sra.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @ashr_v4i32 +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = ashr <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} |
