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| author | Michel Danzer <michel.daenzer@amd.com> | 2013-02-21 08:57:10 +0000 |
|---|---|---|
| committer | Michel Danzer <michel.daenzer@amd.com> | 2013-02-21 08:57:10 +0000 |
| commit | 7f02a8c7a7c1efd07e4f21837b929d14a7c8fd14 (patch) | |
| tree | f1d8958d25a958fac103bf3ee96daa33a8e938c7 /llvm | |
| parent | 3ab4c4ba3045821b8aa5615a7672ca30f017dd10 (diff) | |
| download | bcm5719-llvm-7f02a8c7a7c1efd07e4f21837b929d14a7c8fd14.tar.gz bcm5719-llvm-7f02a8c7a7c1efd07e4f21837b929d14a7c8fd14.zip | |
R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175733
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll | 23 |
2 files changed, 25 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index b4a263d02c7..aef239c7e59 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1311,7 +1311,8 @@ def : Pat < def : Pat < (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params), - (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params) + (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, + (S_MOV_B32 SReg_32:$params)) >; def : Pat < diff --git a/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll new file mode 100644 index 00000000000..0c19f14cc45 --- /dev/null +++ b/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -0,0 +1,23 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: S_MOV_B32 +;CHECK-NEXT: V_INTERP_MOV_F32 + +define void @main() { +main_body: + call void @llvm.AMDGPU.shader.type(i32 0) + %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) + %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0) + %2 = call i32 @llvm.SI.packf16(float %1, float %1) + %3 = bitcast i32 %2 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) + ret void +} + +declare void @llvm.AMDGPU.shader.type(i32) + +declare float @llvm.SI.fs.interp.constant(i32, i32, i32) readonly + +declare i32 @llvm.SI.packf16(float, float) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) |
