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authorHans Wennborg <hans@hanshq.net>2017-12-04 20:39:57 +0000
committerHans Wennborg <hans@hanshq.net>2017-12-04 20:39:57 +0000
commit7e61f249629d3d3d5f5c117f35d914cd3694b963 (patch)
tree0156ba288e54be69bfad3831eae1d750f8017d52 /llvm
parent04e4f47e93e2bc26a80bf738c3692846ca622230 (diff)
downloadbcm5719-llvm-7e61f249629d3d3d5f5c117f35d914cd3694b963.tar.gz
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DAG: Match truncated rotation (PR35487)
If the truncation has been pushed past the or-node, look through it and truncate afterwards. Differential revision: https://reviews.llvm.org/D40792 llvm-svn: 319692
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp9
-rw-r--r--llvm/test/CodeGen/X86/rotate.ll19
2 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5387a7ed73e..30195ff4e91 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4652,6 +4652,15 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
if (!HasROTL && !HasROTR) return nullptr;
+ // Check for truncated rotate.
+ if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE) {
+ assert(LHS.getValueType() == RHS.getValueType());
+ if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
+ return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(),
+ SDValue(Rot, 0)).getNode();
+ }
+ }
+
// Match "(X shl/srl V1) & V2" where V2 may not be present.
SDValue LHSShift; // The shift.
SDValue LHSMask; // AND value if any.
diff --git a/llvm/test/CodeGen/X86/rotate.ll b/llvm/test/CodeGen/X86/rotate.ll
index 6b6c9f0dec3..babe04bafcd 100644
--- a/llvm/test/CodeGen/X86/rotate.ll
+++ b/llvm/test/CodeGen/X86/rotate.ll
@@ -626,3 +626,22 @@ define void @rotr1_8_mem(i8* %Aptr) nounwind {
store i8 %D, i8* %Aptr
ret void
}
+
+define i64 @truncated_rot(i64 %x, i32 %amt) {
+entry:
+ %sh_prom = zext i32 %amt to i64
+ %shl = shl i64 %x, %sh_prom
+ %sub = sub nsw i32 64, %amt
+ %sh_prom1 = zext i32 %sub to i64
+ %shr = lshr i64 %x, %sh_prom1
+ %or = or i64 %shr, %shl
+ %and = and i64 %or, 4294967295
+ ret i64 %and
+
+; 64-LABEL: truncated_rot:
+; 64: # %bb.0:
+; 64-NEXT: movl %esi, %ecx
+; 64-NEXT: rolq %cl, %rdi
+; 64-NEXT: movl %edi, %eax
+; 64-NEXT: retq
+}
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