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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2014-12-11 23:07:52 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2014-12-11 23:07:52 +0000 |
| commit | 79c797443b2e3ebbccaeb7025ce637a9f40452b4 (patch) | |
| tree | 465d5ef87b0c8d253fb1bc9a53bada07a9cf5d04 /llvm | |
| parent | 5c7006e06283a61b26783a8141936466ad3dd3c7 (diff) | |
| download | bcm5719-llvm-79c797443b2e3ebbccaeb7025ce637a9f40452b4.tar.gz bcm5719-llvm-79c797443b2e3ebbccaeb7025ce637a9f40452b4.zip | |
[X86] Add a temporary testcase for PR21876/r223996.
llvm-svn: 224074
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll | 29 |
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index a4af16a14b4..a9ca166c1c7 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6178,6 +6178,7 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> { (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>; // On AVX2, we also support 256bit inputs. + // FIXME: remove these patterns when the old shuffle lowering goes away. def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))), (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))), diff --git a/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll b/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll new file mode 100644 index 00000000000..44eb42adb9f --- /dev/null +++ b/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -x86-experimental-vector-shuffle-lowering=false -mattr=+avx2 | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin" + +; PR21876 +; The old shuffle lowering sometimes generates VZEXT nodes with both input +; and output same-sized types, here 256-bits. For instance, a v8i8 to v8i32 +; zero-extend would become a (v8i32 (VZEXT v32i8)) node, which can't happen +; otherwise. The companion commit r223996 added those patterns temporarily. +; This test, along with the VR256 for AVX2 PMOVXrr instructions, should be +; removed once the old vector shuffle lowering goes away. + +define void @test_avx2_pmovx_256(<8 x i8>* %tmp64, <8 x float>* %tmp75) { +; CHECK-LABEL: test_avx2_pmovx_256 +; We really don't care about the generated code. +; CHECK: vpmovzxbd +; CHECK: vpbroadcastd +; CHECK: vpand +; CHECK: vcvtdq2ps +; CHECK: vmovups +; CHECK: vzeroupper +; CHECK: retq + + %wide.load458 = load <8 x i8>* %tmp64, align 1 + %tmp68 = uitofp <8 x i8> %wide.load458 to <8 x float> + store <8 x float> %tmp68, <8 x float>* %tmp75, align 4 + ret void +} |
