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| author | Marek Olsak <marek.olsak@amd.com> | 2015-01-27 17:25:15 +0000 |
|---|---|---|
| committer | Marek Olsak <marek.olsak@amd.com> | 2015-01-27 17:25:15 +0000 |
| commit | 794ff8392ea1831dd09681fd07e954387f7e17c1 (patch) | |
| tree | 86e50ce5d3b0011a1fbe51a547ff064da1658d34 /llvm | |
| parent | 367447c25551ebfa661956934707084e1cc02ffc (diff) | |
| download | bcm5719-llvm-794ff8392ea1831dd09681fd07e954387f7e17c1.tar.gz bcm5719-llvm-794ff8392ea1831dd09681fd07e954387f7e17c1.zip | |
R600/SI: Fix MIN3/MAX3 on VI, define MED3
llvm-svn: 227213
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 9aeb11322d9..544ea3a1ed2 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1658,27 +1658,34 @@ defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32", VOP_I32_I32_I32_I32 >; -defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32", +defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32", VOP_F32_F32_F32_F32, AMDGPUfmin3>; -defm V_MIN3_I32 : VOP3Inst <vop3<0x152>, "v_min3_i32", +defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32", VOP_I32_I32_I32_I32, AMDGPUsmin3 >; -defm V_MIN3_U32 : VOP3Inst <vop3<0x153>, "v_min3_u32", +defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32", VOP_I32_I32_I32_I32, AMDGPUumin3 >; -defm V_MAX3_F32 : VOP3Inst <vop3<0x154>, "v_max3_f32", +defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32", VOP_F32_F32_F32_F32, AMDGPUfmax3 >; -defm V_MAX3_I32 : VOP3Inst <vop3<0x155>, "v_max3_i32", +defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32", VOP_I32_I32_I32_I32, AMDGPUsmax3 >; -defm V_MAX3_U32 : VOP3Inst <vop3<0x156>, "v_max3_u32", +defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32", VOP_I32_I32_I32_I32, AMDGPUumax3 >; -//def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>; -//def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>; -//def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>; +defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32", + VOP_F32_F32_F32_F32 +>; +defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32", + VOP_I32_I32_I32_I32 +>; +defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32", + VOP_I32_I32_I32_I32 +>; + //def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; //def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; |
