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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-08 14:15:15 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-08 14:15:15 +0000 |
| commit | 7825e064b9c55e024d32ee82749aa4ad30c61214 (patch) | |
| tree | 88c428b8eb6e5f3b9f476f2cdfd57bebc6ac41a1 /llvm | |
| parent | 95f4892d4c09725b436342abe11db4e398e839cc (diff) | |
| download | bcm5719-llvm-7825e064b9c55e024d32ee82749aa4ad30c61214.tar.gz bcm5719-llvm-7825e064b9c55e024d32ee82749aa4ad30c61214.zip | |
Hexagon: Add patterns for zero extended loads from i1->i64.
llvm-svn: 176689
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/zextloadi1.ll | 25 |
3 files changed, 49 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 1e63ed2a9c5..d7bab200f9f 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2875,6 +2875,18 @@ def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1), s11_0ExtPred:$offset)))>, Requires<[NoV4T]>; +// i1 -> i64 +def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)), + (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>, + Requires<[NoV4T]>; + +let AddedComplexity = 20 in +def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1), + s11_0ExtPred:$offset))), + (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1, + s11_0ExtPred:$offset)))>, + Requires<[NoV4T]>; + // i16 -> i64 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)), (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index d5e2d0c71af..1d0643d03b2 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -940,6 +940,18 @@ def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1), s11_0ExtPred:$offset)))>, Requires<[HasV4T]>; +// zext i1->i64 +def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)), + (i64 (COMBINE_Ir_V4 0, (LDriub ADDRriS11_0:$src1)))>, + Requires<[HasV4T]>; + +let AddedComplexity = 20 in +def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1), + s11_0ExtPred:$offset))), + (i64 (COMBINE_Ir_V4 0, (LDriub_indexed IntRegs:$src1, + s11_0ExtPred:$offset)))>, + Requires<[HasV4T]>; + // zext i16->i64 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)), (i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>, diff --git a/llvm/test/CodeGen/Hexagon/zextloadi1.ll b/llvm/test/CodeGen/Hexagon/zextloadi1.ll new file mode 100644 index 00000000000..cb6e6fdf84a --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/zextloadi1.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +; CHECK: r{{[0-9]+}} = ##i129_l+16 +; CHECK: r{{[0-9]+}} = ##i129_s+16 +; CHECK: memd(##i129_s) = r{{[0-9]+:[0-9]+}} +; CHECK: r{{[0-9]+}} = ##i65_l+8 +; CHECK: r{{[0-9]+}} = ##i65_s+8 +; CHECK: memd(##i65_s) = r{{[0-9]+:[0-9]+}} + +@i65_l = external global i65 +@i65_s = external global i65 +@i129_l = external global i129 +@i129_s = external global i129 + +define void @i129_ls() nounwind { + %tmp = load i129* @i129_l + store i129 %tmp, i129* @i129_s + ret void +} + +define void @i65_ls() nounwind { + %tmp = load i65* @i65_l + store i65 %tmp, i65* @i65_s + ret void +}
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