summaryrefslogtreecommitdiffstats
path: root/llvm
diff options
context:
space:
mode:
authorEric Christopher <echristo@apple.com>2010-06-21 20:35:09 +0000
committerEric Christopher <echristo@apple.com>2010-06-21 20:35:09 +0000
commit75d4ecb9c3d74c3ade0d78e78e75873133b17a89 (patch)
tree4d6fa8eabad66c19b2f54fb4f633bc8ef47fdffb /llvm
parent79d2075e4a5a07448135598a40d6ccdeb06613ac (diff)
downloadbcm5719-llvm-75d4ecb9c3d74c3ade0d78e78e75873133b17a89.tar.gz
bcm5719-llvm-75d4ecb9c3d74c3ade0d78e78e75873133b17a89.zip
Remove isTwoAddress from llvm.
llvm-svn: 106470
Diffstat (limited to 'llvm')
-rw-r--r--llvm/docs/TableGenFundamentals.html1
-rw-r--r--llvm/include/llvm/Target/Target.td1
-rw-r--r--llvm/utils/TableGen/CodeGenInstruction.cpp11
3 files changed, 0 insertions, 13 deletions
diff --git a/llvm/docs/TableGenFundamentals.html b/llvm/docs/TableGenFundamentals.html
index 81f3cfe0448..05790e5ae4d 100644
--- a/llvm/docs/TableGenFundamentals.html
+++ b/llvm/docs/TableGenFundamentals.html
@@ -144,7 +144,6 @@ file prints this (at the time of this writing):</p>
<b>bit</b> mayLoad = 0;
<b>bit</b> mayStore = 0;
<b>bit</b> isImplicitDef = 0;
- <b>bit</b> isTwoAddress = 1;
<b>bit</b> isConvertibleToThreeAddress = 1;
<b>bit</b> isCommutable = 1;
<b>bit</b> isTerminator = 0;
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 6379459488f..1d1e1f86130 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -203,7 +203,6 @@ class Instruction {
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
bit mayLoad = 0; // Is it possible for this inst to read memory?
bit mayStore = 0; // Is it possible for this inst to write memory?
- bit isTwoAddress = 0; // Is this a two address instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp
index 99d196c3ceb..35b54a54271 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -107,7 +107,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
mayLoad = R->getValueAsBit("mayLoad");
mayStore = R->getValueAsBit("mayStore");
- bool isTwoAddress = R->getValueAsBit("isTwoAddress");
isPredicable = R->getValueAsBit("isPredicable");
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
isCommutable = R->getValueAsBit("isCommutable");
@@ -212,16 +211,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
// Parse Constraints.
ParseConstraints(R->getValueAsString("Constraints"), this);
- // For backward compatibility: isTwoAddress means operand 1 is tied to
- // operand 0.
- if (isTwoAddress) {
- if (!OperandList[1].Constraints[0].isNone())
- throw R->getName() + ": cannot use isTwoAddress property: instruction "
- "already has constraint set!";
- OperandList[1].Constraints[0] =
- CodeGenInstruction::ConstraintInfo::getTied(0);
- }
-
// Parse the DisableEncoding field.
std::string DisableEncoding = R->getValueAsString("DisableEncoding");
while (1) {
OpenPOWER on IntegriCloud