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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-02-02 17:32:39 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-02-02 17:32:39 +0000 |
| commit | 75c6225f32295ebd9ea7145724bf06c130252bef (patch) | |
| tree | e3a530c31614d0f1d91f242828a5defa3c3ce0b5 /llvm | |
| parent | cf2e21e879333eac8665170135f62199ecd7a4c3 (diff) | |
| download | bcm5719-llvm-75c6225f32295ebd9ea7145724bf06c130252bef.tar.gz bcm5719-llvm-75c6225f32295ebd9ea7145724bf06c130252bef.zip | |
Store fix
llvm-svn: 20004
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 46 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.td | 6 |
2 files changed, 37 insertions, 15 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index a121beb4688..bef34f831c8 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1170,19 +1170,39 @@ void ISel::Select(SDOperand N) { return; case ISD::STORE: - Select(N.getOperand(0)); - Tmp1 = SelectExpr(N.getOperand(1)); //value - if (N.getOperand(2).getOpcode() == ISD::GlobalAddress) - { - AlphaLowering.restoreGP(BB); - BuildMI(BB, Alpha::STORE, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(N.getOperand(2))->getGlobal()); - } - else - { - Tmp2 = SelectExpr(N.getOperand(2)); //address - BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addImm(0).addReg(Tmp2); - } - return; + { + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); //value + MVT::ValueType DestType = N.getOperand(1).getValueType(); + if (N.getOperand(2).getOpcode() == ISD::GlobalAddress) + { + AlphaLowering.restoreGP(BB); + if (DestType == MVT::i64) Opc = Alpha::STORE; + else if (DestType == MVT::f64) Opc = Alpha::STT_SYM; + else if (DestType == MVT::f32) Opc = Alpha::STS_SYM; + else assert(0 && "unknown Type in store"); + BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(N.getOperand(2))->getGlobal()); + } + else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(2))) + { + AlphaLowering.restoreGP(BB); + if (DestType == MVT::i64) Opc = Alpha::STORE; + else if (DestType == MVT::f64) Opc = Alpha::STT_SYM; + else if (DestType == MVT::f32) Opc = Alpha::STS_SYM; + else assert(0 && "unknown Type in store"); + BuildMI(BB, Opc, 2).addReg(Tmp1).addConstantPoolIndex(CP->getIndex()); + } + else + { + Tmp2 = SelectExpr(N.getOperand(2)); //address + if (DestType == MVT::i64) Opc = Alpha::STQ; + else if (DestType == MVT::f64) Opc = Alpha::STT; + else if (DestType == MVT::f32) Opc = Alpha::STS; + else assert(0 && "unknown Type in store"); + BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2); + } + return; + } case ISD::EXTLOAD: case ISD::SEXTLOAD: diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.td b/llvm/lib/Target/Alpha/AlphaInstrInfo.td index b9e2cc34541..ad1d14fc208 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.td +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.td @@ -62,8 +62,10 @@ let Uses = [R29, R28] in { def LOAD : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte - def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load quadword - def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load quadword + def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float + def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double + def STS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "sts $RA,$DISP">; //store float + def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double } let Uses = [R28, R23, R24, R25, R26] in |
