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authorStepan Dyatkovskiy <stpworld@narod.ru>2013-04-05 07:34:08 +0000
committerStepan Dyatkovskiy <stpworld@narod.ru>2013-04-05 07:34:08 +0000
commit6b53a2f50ae13abce43d87dd24521d2dd8d7bbae (patch)
treed795572c354927437c212dfb86637171852f0b8a /llvm
parent734aab406628625706e021143fedb70de8be3f04 (diff)
downloadbcm5719-llvm-6b53a2f50ae13abce43d87dd24521d2dd8d7bbae.tar.gz
bcm5719-llvm-6b53a2f50ae13abce43d87dd24521d2dd8d7bbae.zip
Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage.
llvm-svn: 178854
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 0682459e1cd..b7ac5d57c36 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -103,7 +103,7 @@ namespace {
SmallVector<unsigned, 4> getUnitRegs(unsigned Reg) {
SmallVector<unsigned, 4> Res;
- const TargetRegisterClass* TRC = TRI->getRegClass(Reg);
+ const TargetRegisterClass* TRC = TRI->getMinimalPhysRegClass(Reg);
if (TRC == &ARM::QPRRegClass) {
if (Reg > ARM::Q7) {
Res.push_back(TRI->getSubReg(Reg, ARM::dsub_0));
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