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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-06-11 09:51:58 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-06-11 09:51:58 +0000 |
| commit | 6b0dcd7b8cd44576a1e8f3e5c70ae1235f1650c0 (patch) | |
| tree | 1536a96dca673ca24c5f24c9cc4547b4d7c7cb95 /llvm | |
| parent | fcecf26092c47efb9254177ce5b60529ed414ce2 (diff) | |
| download | bcm5719-llvm-6b0dcd7b8cd44576a1e8f3e5c70ae1235f1650c0.tar.gz bcm5719-llvm-6b0dcd7b8cd44576a1e8f3e5c70ae1235f1650c0.zip | |
[mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312
llvm-svn: 239520
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips-invalid.s | 5 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips32r6/invalid.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips64r6/invalid.s | 4 |
5 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 9c054e5ac23..70025663295 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -879,6 +879,9 @@ public: bool isConstantImm() const { return isImm() && dyn_cast<MCConstantExpr>(getImm()); } + template <unsigned Bits> bool isUImm() const { + return isImm() && isConstantImm() && isUInt<Bits>(getConstantImm()); + } bool isToken() const override { // Note: It's not possible to pretend that other operand kinds are tokens. // The matcher emitter checks tokens first. diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 58791cf2734..cf95a194f47 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -384,7 +384,15 @@ def simm20 : Operand<i32> { def uimm20 : Operand<i32> { } +def MipsUImm10AsmOperand : AsmOperandClass { + let Name = "UImm10"; + let RenderMethod = "addImmOperands"; + let ParserMethod = "parseImm"; + let PredicateMethod = "isUImm<10>"; +} + def uimm10 : Operand<i32> { + let ParserMatchClass = MipsUImm10AsmOperand; } def simm16_64 : Operand<i64> { diff --git a/llvm/test/MC/Mips/micromips-invalid.s b/llvm/test/MC/Mips/micromips-invalid.s index 4321574b5bf..74a62ceeba0 100644 --- a/llvm/test/MC/Mips/micromips-invalid.s +++ b/llvm/test/MC/Mips/micromips-invalid.s @@ -73,3 +73,8 @@ movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips32r6/invalid.s b/llvm/test/MC/Mips/mips32r6/invalid.s index 82cb5ab4943..0ce75e6143c 100644 --- a/llvm/test/MC/Mips/mips32r6/invalid.s +++ b/llvm/test/MC/Mips/mips32r6/invalid.s @@ -12,3 +12,7 @@ ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s index 1b01827368a..ae980347f30 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid.s +++ b/llvm/test/MC/Mips/mips64r6/invalid.s @@ -10,3 +10,7 @@ jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction |
