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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-24 16:12:31 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-24 16:12:31 +0000 |
| commit | 6aac6463088f8a3fca80aadaf4dd32d1128a2553 (patch) | |
| tree | dea953589d50a3299da4aa5f70388c9a79c8457b /llvm | |
| parent | dd0620ed97cab731708d55dd15555b0d828e606d (diff) | |
| download | bcm5719-llvm-6aac6463088f8a3fca80aadaf4dd32d1128a2553.tar.gz bcm5719-llvm-6aac6463088f8a3fca80aadaf4dd32d1128a2553.zip | |
[X86][SSE] Generalised lowerTruncate by PACKSS to work with any 'zero/all bits' result, not just comparisons.
Added vector compare opcodes to X86TargetLowering::ComputeNumSignBitsForTargetNode
Covered by existing tests added for D22814.
llvm-svn: 298704
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 36 |
1 files changed, 19 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8c8a5ed6f1a..4b807ebcba8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15791,20 +15791,10 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(X86ISD::VTRUNC, DL, VT, In); } - // Truncate with PACKSS if we are truncating a vector comparison result. - // TODO: We should be able to support other operations as long as we - // we are saturating+packing zero/all bits only. - auto IsPackableComparison = [](SDValue V) { - unsigned Opcode = V.getOpcode(); - return (Opcode == X86ISD::PCMPGT || Opcode == X86ISD::PCMPEQ || - Opcode == X86ISD::CMPP); - }; - - if (IsPackableComparison(In) || (In.getOpcode() == ISD::CONCAT_VECTORS && - all_of(In->ops(), IsPackableComparison))) { + // Truncate with PACKSS if we are truncating a vector zero/all-bits result. + if (InVT.getScalarSizeInBits() == DAG.ComputeNumSignBits(In)) if (SDValue V = truncateVectorCompareWithPACKSS(VT, In, DL, DAG, Subtarget)) return V; - } if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) { // On AVX2, v4i64 -> v4i32 becomes VPERMD. @@ -26640,18 +26630,30 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode( SDValue Op, const SelectionDAG &DAG, unsigned Depth) const { - // SETCC_CARRY sets the dest to ~0 for true or 0 for false. - if (Op.getOpcode() == X86ISD::SETCC_CARRY) + unsigned Opcode = Op.getOpcode(); + switch (Opcode) { + case X86ISD::SETCC_CARRY: + // SETCC_CARRY sets the dest to ~0 for true or 0 for false. return Op.getScalarValueSizeInBits(); - if (Op.getOpcode() == X86ISD::VSEXT) { + case X86ISD::VSEXT: { + SDValue Src = Op.getOperand(0); EVT VT = Op.getValueType(); - EVT SrcVT = Op.getOperand(0).getValueType(); - unsigned Tmp = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1); + EVT SrcVT = Src.getValueType(); + unsigned Tmp = DAG.ComputeNumSignBits(Src, Depth + 1); Tmp += VT.getScalarSizeInBits() - SrcVT.getScalarSizeInBits(); return Tmp; } + case X86ISD::PCMPGT: + case X86ISD::PCMPEQ: + case X86ISD::CMPP: + case X86ISD::VPCOM: + case X86ISD::VPCOMU: + // Vector compares return zero/all-bits result values. + return Op.getScalarValueSizeInBits(); + } + // Fallback case. return 1; } |

