Don't produce ADDC/ADDE when expanding SHL unless they are legal

for the target. This fixes PR3080.

llvm-svn: 59450

2 files changed, 8 insertions, 1 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index fb05f334c09..ddc339c324f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1073,7 +1073,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
     } else if (Amt == NVTBits) {
       Lo = DAG.getConstant(0, NVT);
       Hi = InL;
-    } else if (Amt == 1) {
+    } else if (Amt == 1 &&
+               TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
       // Emit this X << 1 as X+X.
       SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };
diff --git a/llvm/test/CodeGen/XCore/2008-11-17-Shl64.ll b/llvm/test/CodeGen/XCore/2008-11-17-Shl64.ll
new file mode 100644
index 00000000000..97ea41b8d0c
--- /dev/null
+++ b/llvm/test/CodeGen/XCore/2008-11-17-Shl64.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc -march=xcore > %t1.s
+; PR3080
+define i64 @test(i64 %a) {
+	%result = shl i64 %a, 1
+	ret i64 %result
+}