move loads and stores over. Smart addr selection comming

llvm-svn: 25000

3 files changed, 53 insertions, 58 deletions

diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 011b94b0abc..f570fa6a39a 100644
--- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -35,7 +35,6 @@ namespace {
   //===--------------------------------------------------------------------===//
   /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
   /// instructions for SelectionDAG operations.
-  ///
   class AlphaDAGToDAGISel : public SelectionDAGISel {
     AlphaTargetLowering AlphaLowering;
 
@@ -194,63 +193,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
     return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, 
                                 CurDAG->getBasicBlock(Dest), Chain);
   }
-  case ISD::LOAD:
-  case ISD::EXTLOAD:
-  case ISD::ZEXTLOAD:
-  case ISD::SEXTLOAD: {
-    SDOperand Chain = Select(N->getOperand(0));
-    SDOperand Address = Select(N->getOperand(1));
-    unsigned opcode = N->getOpcode();
-    unsigned Opc = Alpha::WTF;
-    if (opcode == ISD::LOAD)
-      switch (N->getValueType(0)) {
-      default: N->dump(); assert(0 && "Bad load!");
-      case MVT::i64: Opc = Alpha::LDQ; break;
-      case MVT::f64: Opc = Alpha::LDT; break;
-      case MVT::f32: Opc = Alpha::LDS; break;
-      }
-    else
-      switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
-      default: N->dump(); assert(0 && "Bad sign extend!");
-      case MVT::i32: Opc = Alpha::LDL;
-        assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
-      case MVT::i16: Opc = Alpha::LDWU;
-        assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
-      case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
-      case MVT::i8: Opc = Alpha::LDBU;
-          assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
-      }
-
-    return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
-                                getI64Imm(0), Address, 
-                                Chain).getValue(Op.ResNo);
-  }
-  case ISD::STORE:
-  case ISD::TRUNCSTORE: {
-    SDOperand Chain = Select(N->getOperand(0));
-    SDOperand Value = Select(N->getOperand(1));
-    SDOperand Address = Select(N->getOperand(2));
-
-    unsigned Opc = Alpha::WTF;
-
-    if (N->getOpcode() == ISD::STORE) {
-      switch (N->getOperand(1).getValueType()) {
-      case MVT::i64: Opc = Alpha::STQ; break;
-      case MVT::f64: Opc = Alpha::STT; break;
-      case MVT::f32: Opc = Alpha::STS; break;
-      default: assert(0 && "Bad store!");
-      };
-    } else { //TRUNCSTORE
-      switch (cast<VTSDNode>(N->getOperand(4))->getVT()) {
-      case MVT::i32: Opc = Alpha::STL; break;
-      case MVT::i16: Opc = Alpha::STW; break;
-      case MVT::i8: Opc = Alpha::STB; break;
-      default: assert(0 && "Bad truncstore!");
-      };
-    }
-    return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0),
-                                Address, Chain);
-  }
 
   case ISD::BR: 
     return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
diff --git a/llvm/lib/Target/Alpha/AlphaInstrFormats.td b/llvm/lib/Target/Alpha/AlphaInstrFormats.td
index cf7df80085c..674a259fe1d 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrFormats.td
+++ b/llvm/lib/Target/Alpha/AlphaInstrFormats.td
@@ -40,6 +40,18 @@ class InstAlpha<bits<6> op, dag OL, string asmstr>
 }
 
 //3.3.1
+class MFormD<bits<6> opcode, string asmstr, list<dag> pattern> 
+        : InstAlphaAlt<opcode, asmstr> {
+  let Pattern = pattern;
+
+  bits<5> Ra;
+  bits<16> disp;
+  bits<5> Rb;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-16} = Rb;
+  let Inst{15-0} = disp;
+}
 class MFormAlt<bits<6> opcode, string asmstr> 
         : InstAlphaAlt<opcode, asmstr> {
   bits<5> Ra;
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.td b/llvm/lib/Target/Alpha/AlphaInstrInfo.td
index d0109cad16c..75fa67c408a 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.td
@@ -436,6 +436,47 @@ def BR : BForm<0x30, "br $RA,$DISP">; //Branch
 
 def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch
 
+
+let isLoad = 1, OperandList = (ops GPRC:$RA, GPRC:$RB), disp = 0 in {
+def LDQdag : MFormD<0x29,  "ldq $RA,0($RB)",
+                    [(set GPRC:$RA, (load GPRC:$RB))]>;
+def LDLdag : MFormD<0x29,  "ldl $RA,0($RB)",
+                    [(set GPRC:$RA, (sextload GPRC:$RB, i32))]>;
+def LDBUdag : MFormD<0x0A, "ldbu $RA,0($RB)",
+                    [(set GPRC:$RA, (zextload GPRC:$RB, i8))]>;
+def LDWUdag : MFormD<0x0C, "ldwu $RA,0($RB)",
+                    [(set GPRC:$RA, (zextload GPRC:$RB, i16))]>;
+
+def STBdag : MFormD<0x0E, "stb $RA,0($RB)",
+		    [(truncstore GPRC:$RA, GPRC:$RB, i8)]>;
+def STWdag : MFormD<0x0D, "stw $RA,0($RB)",
+		    [(truncstore GPRC:$RA, GPRC:$RB, i16)]>;
+def STLdag : MFormD<0x2C, "stl $RA,0($RB)",
+		    [(truncstore GPRC:$RA, GPRC:$RB, i32)]>;
+def STQdag : MFormD<0x2D, "stq $RA,0($RB)",
+		    [(store GPRC:$RA, GPRC:$RB)]>;
+}
+
+def : Pat<(i64 (extload GPRC:$src, i8)),
+          (LDBUdag GPRC:$src)>;
+def : Pat<(i64 (extload GPRC:$src, i16)),
+          (LDWUdag GPRC:$src)>;
+def : Pat<(i64 (extload GPRC:$src, i32)),
+          (LDLdag GPRC:$src)>;
+
+let isLoad = 1, OperandList = (ops F4RC:$RA, GPRC:$RB), disp = 0 in {
+def STSdag : MFormD<0x26, "sts $RA,0($RB)",
+		[(store F4RC:$RA, GPRC:$RB)]>;
+def LDSdag : MFormD<0x22, "lds $RA,0($RB)",
+		[(set F4RC:$RA, (load GPRC:$RB))]>;
+}
+let isLoad = 1, OperandList = (ops F8RC:$RA, GPRC:$RB), disp = 0 in {
+def STTdag : MFormD<0x27, "stt $RA,0($RB)",
+		[(store F8RC:$RA, GPRC:$RB)]>;
+def LDTdag : MFormD<0x23, "ldt $RA,0($RB)",
+		[(set F8RC:$RA, (load GPRC:$RB))]>;
+}
+
 //Stores, int
 def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
 def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word