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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-12-13 08:27:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-12-13 08:27:48 +0000 |
| commit | 577b9fc54370b51262b11f5fee7474e9c71f4507 (patch) | |
| tree | f43ef093c8df68c4d7e11497aeb44ff4f9fa68b9 /llvm | |
| parent | fa81940fc71ab334e8ea09a64338a7f11d814867 (diff) | |
| download | bcm5719-llvm-577b9fc54370b51262b11f5fee7474e9c71f4507.tar.gz bcm5719-llvm-577b9fc54370b51262b11f5fee7474e9c71f4507.zip | |
AMDGPU/GlobalISel: Legalize f64 fadd/fmul
llvm-svn: 349014
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir | 17 |
3 files changed, 31 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 65513d7993c..83e8504bfd7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -88,14 +88,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, // between these two scenarios. setAction({G_CONSTANT, S1}, Legal); - setAction({G_FADD, S32}, Legal); + getActionDefinitionsBuilder( + { G_FADD, G_FMUL }) + .legalFor({S32, S64}); setAction({G_FCMP, S1}, Legal); setAction({G_FCMP, 1, S32}, Legal); setAction({G_FCMP, 1, S64}, Legal); - setAction({G_FMUL, S32}, Legal); - setAction({G_ZEXT, S64}, Legal); setAction({G_ZEXT, 1, S32}, Legal); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir index 6597eea3f7e..85ed234bf47 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir @@ -1,7 +1,7 @@ # RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s --- -name: test_fadd +name: test_fadd_f32 body: | bb.0.entry: liveins: $vgpr0, $vgpr1 @@ -13,3 +13,14 @@ body: | %2:_(s32) = G_FADD %0, %1 $vgpr0 = COPY %2 ... +--- +name: test_fadd_f64 +body: | + bb.0.entry: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s64) = G_FADD %0, %1 + $vgpr0_vgpr1 = COPY %2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir index 361e9af2a86..8a0ce1c6e91 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s --- -name: test_fmul +name: test_fmul_f32 body: | bb.0: liveins: $vgpr0, $vgpr1 @@ -16,3 +16,18 @@ body: | %2:_(s32) = G_FMUL %0, %1 $vgpr0 = COPY %2 ... +--- +name: test_fmul_f64 +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: test_fmul + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]] + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s64) = G_FMUL %0, %1 + $vgpr0_vgpr1 = COPY %2 +... |
