[CodeGenPrepare] Respect endianness in splitMergedValStore.

splitMergedValStore will split a store into two if target prefers this, or if
-force-split-store is passed.

This patch adds the missing handling for endianness in this function along
with a test case.

Review: Eli Friedman
https://reviews.llvm.org/D44396

llvm-svn: 327375

2 files changed, 24 insertions, 1 deletions

diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 422a0a972fb..b8922bd8ed8 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -5999,12 +5999,13 @@ static bool splitMergedValStore(StoreInst &SI, const DataLayout &DL,
   if (HBC && HBC->getParent() != SI.getParent())
     HValue = Builder.CreateBitCast(HBC->getOperand(0), HBC->getType());
 
+  bool IsLE = SI.getModule()->getDataLayout().isLittleEndian();
   auto CreateSplitStore = [&](Value *V, bool Upper) {
     V = Builder.CreateZExtOrBitCast(V, SplitStoreType);
     Value *Addr = Builder.CreateBitCast(
         SI.getOperand(1),
         SplitStoreType->getPointerTo(SI.getPointerAddressSpace()));
-    if (Upper)
+    if ((IsLE && Upper) || (!IsLE && !Upper))
       Addr = Builder.CreateGEP(
           SplitStoreType, Addr,
           ConstantInt::get(Type::getInt32Ty(SI.getContext()), 1));
diff --git a/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll b/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll
new file mode 100644
index 00000000000..0b1e2b477c2
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll
@@ -0,0 +1,22 @@
+; Test that CodeGenPrepare respects endianness when splitting a store.
+;
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -force-split-store < %s  | FileCheck %s
+
+define void @fun(i16* %Src, i16* %Dst) {
+; CHECK-LABEL: # %bb.0:
+; CHECK:       lh   %r0, 0(%r2)
+; CHECK-NEXT:  stc  %r0, 1(%r3)
+; CHECK-NEXT:  srl  %r0, 8
+; CHECK-NEXT:  stc  %r0, 0(%r3)
+; CHECK-NEXT:  br   %r14
+  %1 = load i16, i16* %Src
+  %2 = trunc i16 %1 to i8
+  %3 = lshr i16 %1, 8
+  %4 = trunc i16 %3 to i8
+  %5 = zext i8 %2 to i16
+  %6 = zext i8 %4 to i16
+  %7 = shl nuw i16 %6, 8
+  %8 = or i16 %7, %5
+  store i16 %8, i16* %Dst
+  ret void
+}