[Hexagon] Remove icmp undef from reduced tests

Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC)

Approved by @kparzysz (Krzysztof Parzyszek)

llvm-svn: 356267

10 files changed, 18 insertions, 18 deletions

diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
index 587383b7e18..4e49162dec4 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
@@ -11,7 +11,7 @@ define hidden fastcc void @fred(i32 %a0) #0 {
 b1:
   %v2 = insertelement <32 x i32> undef, i32 %a0, i32 0
   %v3 = shufflevector <32 x i32> %v2, <32 x i32> undef, <32 x i32> zeroinitializer
-  %v4 = icmp eq <32 x i32> %v3, undef
+  %v4 = icmp eq <32 x i32> %v2, %v3
   %v5 = and <32 x i1> undef, %v4
   br label %b6
 
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
index e9150c6b93b..af5737675d3 100644
--- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
@@ -2,7 +2,7 @@
 ; REQUIRES: asserts
 
 ; Check for some output (as opposed to a crash).
-; CHECK: loop0
+; CHECK: fred
 
 target triple = "hexagon"
 
diff --git a/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll b/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll
index d3dc7e7e213..8cb5cffc0ed 100644
--- a/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll
+++ b/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll
@@ -128,7 +128,7 @@ b24:                                              ; preds = %b23, %b19
   br label %b25
 
 b25:                                              ; preds = %b24
-  %v28 = icmp sgt i64 undef, %v27
+  %v28 = icmp sgt i64 0, %v27
   br i1 %v28, label %b28, label %b26
 
 b26:                                              ; preds = %b25
diff --git a/llvm/test/CodeGen/Hexagon/redundant-branching2.ll b/llvm/test/CodeGen/Hexagon/redundant-branching2.ll
index 36505974d62..50007007d17 100644
--- a/llvm/test/CodeGen/Hexagon/redundant-branching2.ll
+++ b/llvm/test/CodeGen/Hexagon/redundant-branching2.ll
@@ -13,7 +13,7 @@ target triple = "hexagon-unknown--elf"
 declare void @f0() #0
 
 ; Function Attrs: nounwind
-define void @f1(i8* %a0, i32 %a1, i8* %a2, i32* %a3) #0 {
+define void @f1(i8* %a0, i32 %a1, i8* %a2, i32* %a3, i32 %a4) #0 {
 b0:
   br i1 undef, label %b8, label %b1
 
@@ -24,7 +24,7 @@ b1:                                               ; preds = %b0
 b2:                                               ; preds = %b1
   %v0 = getelementptr inbounds i8, i8* %a0, i32 undef
   %v1 = sub i32 0, %a1
-  %v2 = icmp eq i32 undef, undef
+  %v2 = icmp eq i32 %a1, %a4
   br label %b3
 
 b3:                                               ; preds = %b6, %b2
@@ -61,7 +61,7 @@ b6:                                               ; preds = %b5, %b4
   %v24 = add nuw nsw i32 %v23, %v19
   %v25 = add nsw i32 %v24, 0
   store i32 %v25, i32* %a3, align 4
-  %v26 = icmp eq i32 %v5, undef
+  %v26 = icmp eq i32 %v5, %a4
   br i1 %v26, label %b7, label %b3
 
 b7:                                               ; preds = %b6
diff --git a/llvm/test/CodeGen/Hexagon/swp-change-deps.ll b/llvm/test/CodeGen/Hexagon/swp-change-deps.ll
index 4eebfb6d6f5..e2ca071f5f5 100644
--- a/llvm/test/CodeGen/Hexagon/swp-change-deps.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-change-deps.ll
@@ -23,7 +23,7 @@ declare i32 @llvm.hexagon.A2.addsat(i32, i32) #1
 ; Function Attrs: nounwind readnone
 declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #1
 
-define void @f0() #0 align 2 {
+define void @f0(i32 %a0) #0 align 2 {
 b0:
   br label %b1
 
@@ -46,7 +46,7 @@ b2:                                               ; preds = %b2, %b1
   %v11 = trunc i32 %v7 to i16
   store i16 %v11, i16* %v0, align 2
   %v12 = add nsw i32 %v1, 1
-  %v13 = icmp slt i32 %v12, undef
+  %v13 = icmp slt i32 %v12, %a0
   %v14 = getelementptr i16, i16* %v0, i32 1
   br i1 %v13, label %b2, label %b3
 
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll
index 36805c89037..b2a7dada33f 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll
@@ -14,7 +14,7 @@
 %s.11 = type { i32, i32, i8* }
 
 ; Function Attrs: nounwind
-define void @f0(%s.0* %a0, i8* %a1, i16* %a2, i16** %a3, i16** %a4) #0 {
+define void @f0(%s.0* %a0, i8* %a1, i16* %a2, i16** %a3, i16** %a4, i32 %a5) #0 {
 b0:
   %v0 = load i8, i8* %a1, align 1, !tbaa !0
   %v1 = icmp eq i8 %v0, 1
@@ -47,7 +47,7 @@ b1:                                               ; preds = %b1, %b0
   store i16* %v17, i16** %a4, align 4, !tbaa !3
   store i16 0, i16* %v16, align 2, !tbaa !5
   %v18 = add nsw i32 %v3, 8
-  %v19 = icmp slt i32 %v18, undef
+  %v19 = icmp slt i32 %v18, %a5
   br i1 %v19, label %b1, label %b2
 
 b2:                                               ; preds = %b1, %b0
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
index 2e268d74b93..15e63e19e45 100644
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
@@ -12,7 +12,7 @@
 ; CHECK: [[REG0]] = add(r{{[0-9]+}},#8)
 
 ; Function Attrs: nounwind
-define void @f0(i16* nocapture readonly %a0) #0 {
+define void @f0(i16* nocapture readonly %a0, i32 %a1) #0 {
 b0:
   %v0 = alloca [129 x i32], align 8
   br i1 undef, label %b1, label %b3
@@ -37,7 +37,7 @@ b2:                                               ; preds = %b2, %b1
   %v13 = add i32 %v5, 1
   %v14 = getelementptr inbounds i32, i32* %v3, i32 2
   %v15 = getelementptr inbounds i16, i16* %v1, i32 2
-  %v16 = icmp slt i32 %v13, undef
+  %v16 = icmp slt i32 %v13, %a1
   br i1 %v16, label %b2, label %b3
 
 b3:                                               ; preds = %b2, %b0
diff --git a/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll b/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
index 288f61864d7..4a6fa5a6cfe 100644
--- a/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll
@@ -9,7 +9,7 @@
 ; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
 ; CHECK: loop0
 
-define void @f0(<64 x i32> %a0, <32 x i32> %a1) #0 {
+define void @f0(<64 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
 b0:
   br i1 undef, label %b1, label %b5
 
@@ -29,7 +29,7 @@ b3:                                               ; preds = %b3, %b2
   %v6 = tail call <1024 x i1> @llvm.hexagon.V6.veqh.and.128B(<1024 x i1> %v5, <32 x i32> undef, <32 x i32> undef)
   %v7 = tail call <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<1024 x i1> %v6, <32 x i32> %v4, <32 x i32> undef)
   %v8 = add nsw i32 %v2, 1
-  %v9 = icmp slt i32 %v8, undef
+  %v9 = icmp slt i32 %v8, %a2
   br i1 %v9, label %b3, label %b4
 
 b4:                                               ; preds = %b3
diff --git a/llvm/test/CodeGen/Hexagon/swp-rename.ll b/llvm/test/CodeGen/Hexagon/swp-rename.ll
index 7f5060134f4..ab0cc11ec7e 100644
--- a/llvm/test/CodeGen/Hexagon/swp-rename.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-rename.ll
@@ -7,9 +7,9 @@
 ; CHECK: .LBB0_[[LOOP]]:
 ; CHECK: memh([[REG0]]+#0) = #0
 
-define void @f0() #0 {
+define void @f0(i32 %a0) #0 {
 b0:
-  %v0 = add i32 undef, -4
+  %v0 = add i32 %a0, -4
   br label %b1
 
 b1:                                               ; preds = %b1, %b0
diff --git a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll
index 652a000fd7a..f6110308011 100644
--- a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll
+++ b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll
@@ -14,10 +14,10 @@ target triple = "hexagon"
 
 declare hidden fastcc void @foo(%struct.0* noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0
 
-define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval nocapture readonly align 8 %a) #1 {
+define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval nocapture readonly align 8 %a, i32 %a0) #1 {
 entry:
   %0 = load i64, i64* undef, align 8
-  switch i32 undef, label %if.else [
+  switch i32 %a0, label %if.else [
     i32 32767, label %if.then
     i32 0, label %if.then7
   ]