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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-01 02:02:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-01 02:02:21 +0000 |
| commit | 51d2d0f668ba2e2b52fc20f44fc4d60005c55a13 (patch) | |
| tree | 7c9b3a31df4620ff71457ac7c1a1b50ef7f46fc3 /llvm | |
| parent | 86f14e09a667735d5bd63b77c1412d8fa322aa29 (diff) | |
| download | bcm5719-llvm-51d2d0f668ba2e2b52fc20f44fc4d60005c55a13.tar.gz bcm5719-llvm-51d2d0f668ba2e2b52fc20f44fc4d60005c55a13.zip | |
AMDGPU: Fix adding redundant implicit operands
These are already added during the MachineInstr construction,
so this was adding the implicit registers twice.
llvm-svn: 246525
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 52d0fc3ac24..80b541061e3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1881,19 +1881,15 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); // NewVaddrLo = SRsrcPtrLo + VAddr:sub0 - BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32), - NewVAddrLo) - .addReg(SRsrcPtrLo) - .addReg(VAddr->getReg(), 0, AMDGPU::sub0) - .addReg(AMDGPU::VCC, RegState::ImplicitDefine); + DebugLoc DL = MI->getDebugLoc(); + BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo) + .addReg(SRsrcPtrLo) + .addReg(VAddr->getReg(), 0, AMDGPU::sub0); // NewVaddrHi = SRsrcPtrHi + VAddr:sub1 - BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32), - NewVAddrHi) - .addReg(SRsrcPtrHi) - .addReg(VAddr->getReg(), 0, AMDGPU::sub1) - .addReg(AMDGPU::VCC, RegState::ImplicitDefine) - .addReg(AMDGPU::VCC, RegState::Implicit); + BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi) + .addReg(SRsrcPtrHi) + .addReg(VAddr->getReg(), 0, AMDGPU::sub1); } else { // This instructions is the _OFFSET variant, so we need to convert it to |
