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| author | Nirav Dave <niravd@google.com> | 2017-06-19 15:18:20 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-06-19 15:18:20 +0000 |
| commit | 4e363e36fb4b17c828166f13dde6c880496ae134 (patch) | |
| tree | af62af5ac43f8c1e3260e8b01b0c1627adb09bb2 /llvm | |
| parent | 5f07f443be954e2d4feed14eb6ea573f0d4e5d01 (diff) | |
| download | bcm5719-llvm-4e363e36fb4b17c828166f13dde6c880496ae134.tar.gz bcm5719-llvm-4e363e36fb4b17c828166f13dde6c880496ae134.zip | |
Add test for store merge with noimplicitfloat
llvm-svn: 305697
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll b/llvm/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll new file mode 100644 index 00000000000..74aeaf75d03 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll @@ -0,0 +1,23 @@ +; RUN: llc -o - %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios10.0.0" + +; PR33475 - Expect 64-bit operations as 128-operations are not legal + +; CHECK-LABEL: pr33475 +; CHECK-DAG: ldr [[R0:x[0-9]+]], [x1] +; CHECK-DAG: str [[R0]], [x0] +; CHECK-DAG: ldr [[R1:x[0-9]+]], [x1, #8] +; CHECK-DAG: str [[R1]], [x0, #8] +; CHECK-DAG: ldr [[R2:x[0-9]+]], [x1, #16] +; CHECK-DAG: str [[R2]], [x0, #16] +; CHECK-DAG: ldr [[R3:x[0-9]+]], [x1, #24] +; CHECK-DAG: str [[R3]], [x0, #24] + +define void @pr33475(i8* %p0, i8* %p1) noimplicitfloat { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p0, i8* %p1, i64 32, i32 4, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) |
