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authorDaniel Sanders <daniel_l_sanders@apple.com>2017-11-01 22:13:05 +0000
committerDaniel Sanders <daniel_l_sanders@apple.com>2017-11-01 22:13:05 +0000
commit466fe399b87e3e9fac2bbe853e2200b4b146a5b3 (patch)
tree7c22c569f3ded891e026df003f4dcb874fd5033a /llvm
parentcf82cc3d54108c4d67a954a6cf4905c262a65197 (diff)
downloadbcm5719-llvm-466fe399b87e3e9fac2bbe853e2200b4b146a5b3.tar.gz
bcm5719-llvm-466fe399b87e3e9fac2bbe853e2200b4b146a5b3.zip
[globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.
llvm-svn: 317132
Diffstat (limited to 'llvm')
-rw-r--r--llvm/include/llvm/TableGen/Error.h2
-rw-r--r--llvm/lib/TableGen/Error.cpp4
-rw-r--r--llvm/utils/TableGen/RegisterBankEmitter.cpp13
3 files changed, 19 insertions, 0 deletions
diff --git a/llvm/include/llvm/TableGen/Error.h b/llvm/include/llvm/TableGen/Error.h
index 3df658df880..de4d3bf5478 100644
--- a/llvm/include/llvm/TableGen/Error.h
+++ b/llvm/include/llvm/TableGen/Error.h
@@ -19,6 +19,8 @@
namespace llvm {
+void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg);
+
void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg);
void PrintWarning(const char *Loc, const Twine &Msg);
void PrintWarning(const Twine &Msg);
diff --git a/llvm/lib/TableGen/Error.cpp b/llvm/lib/TableGen/Error.cpp
index fd089356625..b4830178a26 100644
--- a/llvm/lib/TableGen/Error.cpp
+++ b/llvm/lib/TableGen/Error.cpp
@@ -39,6 +39,10 @@ static void PrintMessage(ArrayRef<SMLoc> Loc, SourceMgr::DiagKind Kind,
"instantiated from multiclass");
}
+void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg) {
+ PrintMessage(NoteLoc, SourceMgr::DK_Note, Msg);
+}
+
void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg) {
PrintMessage(WarningLoc, SourceMgr::DK_Warning, Msg);
}
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 293933ffb8d..5c647168804 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -299,6 +299,19 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
Banks.push_back(Bank);
}
+ // Warn about ambiguous MIR caused by register bank/class name clashes.
+ for (const auto &Class : Records.getAllDerivedDefinitions("RegisterClass")) {
+ for (const auto &Bank : Banks) {
+ if (Bank.getName().lower() == Class->getName().lower()) {
+ PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
+ "distinct from register classes "
+ "to avoid ambiguous MIR");
+ PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
+ PrintNote(Class->getLoc(), "RegisterClass was declared here");
+ }
+ }
+ }
+
emitSourceFileHeader("Register Bank Source Fragments", OS);
OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
<< "#undef GET_REGBANK_DECLARATIONS\n";
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