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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-23 13:24:17 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-23 13:24:17 +0000 |
| commit | 455d0b2cfee4b3203207a0748b7f12fe85be24a9 (patch) | |
| tree | a6bc1d06c255b294ae654919d8b9ea12149d65bd /llvm | |
| parent | 77c5471d9f4523d0a2f56771ad07dffd6655f7ff (diff) | |
| download | bcm5719-llvm-455d0b2cfee4b3203207a0748b7f12fe85be24a9.tar.gz bcm5719-llvm-455d0b2cfee4b3203207a0748b7f12fe85be24a9.zip | |
[X86] Remove instregex matching from CLAC/STAC.
Note - noticed this as the STAC case as it was unintentionally matching against *STACK* pseudo instructions.
llvm-svn: 330588
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 6 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 6 |
2 files changed, 4 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 5b64ccccb17..ce272b26465 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -450,7 +450,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO)>; +def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "ADC(16|32|64)i", "ADC(8|16|32|64)rr", @@ -464,7 +464,6 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "CLAC", "RORX(32|64)ri", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", @@ -477,8 +476,7 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "SHLX(32|64)rr", "SHR(8|16|32|64)r1", "SHR(8|16|32|64)ri", - "SHRX(32|64)rr", - "STAC")>; + "SHRX(32|64)rr")>; def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index eeb5d4d6987..5e766088d7c 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -755,7 +755,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO)>; +def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "ADC(16|32|64)i", "ADC(8|16|32|64)rr", @@ -769,7 +769,6 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "CLAC", "RORX(32|64)ri", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", @@ -782,8 +781,7 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "SHLX(32|64)rr", "SHR(8|16|32|64)r1", "SHR(8|16|32|64)ri", - "SHRX(32|64)rr", - "STAC")>; + "SHRX(32|64)rr")>; def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { let Latency = 1; |
