Use Evan's outflag stuff to implement V8cmpicc. This allows us to write a

pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.

llvm-svn: 25212

2 files changed, 27 insertions, 16 deletions

diff --git a/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index 1ef719558ae..4b927896a0d 100644
--- a/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -635,10 +635,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     
     // Get the condition flag.
     if (LHS.getValueType() == MVT::i32) {
-      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
+      std::vector<MVT::ValueType> VTs;
+      VTs.push_back(MVT::i32);
+      VTs.push_back(MVT::Flag);
+      std::vector<SDOperand> Ops;
+      Ops.push_back(LHS);
+      Ops.push_back(RHS);
+      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops);
       return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
     } else {
-      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
+      std::vector<MVT::ValueType> VTs;
+      VTs.push_back(MVT::i32);
+      VTs.push_back(MVT::Flag);
+      std::vector<SDOperand> Ops;
+      Ops.push_back(LHS);
+      Ops.push_back(RHS);
+      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops);
       return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
     }
   }
@@ -651,7 +663,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     
     unsigned Opc;
     Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
-    SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
+    std::vector<MVT::ValueType> VTs;
+    VTs.push_back(LHS.getValueType());
+    VTs.push_back(MVT::Flag);
+    std::vector<SDOperand> Ops;
+    Ops.push_back(LHS);
+    Ops.push_back(RHS);
+    SDOperand CompareFlag = DAG.getNode(Opc, VTs, Ops).getValue(1);
     
     Opc = LHS.getValueType() == MVT::i32 ? 
       V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
@@ -883,14 +901,6 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
                             CurDAG->getTargetFrameIndex(FI, MVT::i32),
                             CurDAG->getTargetConstant(0, MVT::i32));
   }
-  case V8ISD::CMPICC: {
-    // FIXME: Handle compare with immediate.
-    SDOperand LHS = Select(N->getOperand(0));
-    SDOperand RHS = Select(N->getOperand(1));
-    SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
-                                             LHS, RHS);
-    return CodeGenMap[Op] = Result.getValue(1);
-  }
   case ISD::ADD_PARTS: {
     SDOperand LHSL = Select(N->getOperand(0));
     SDOperand LHSH = Select(N->getOperand(1));
diff --git a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
index bbba1fcba41..6314aba35f1 100644
--- a/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -59,8 +59,6 @@ def MEMri : Operand<i32> {
 def brtarget : Operand<OtherVT>;
 def calltarget : Operand<i32>;
 
-def SDTV8cmpicc : 
-SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
 def SDTV8cmpfcc : 
 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
 def SDTV8brcc : 
@@ -74,7 +72,8 @@ SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
 def SDTV8ITOF :
 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
 
-def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
+def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp,
+                      [SDNPCommutative, SDNPOutFlag]>;
 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
@@ -405,10 +404,12 @@ def SUBXri  : F3_2<2, 0b001100,
                    "subx $b, $c, $dst", []>;
 def SUBCCrr : F3_1<2, 0b010100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "subcc $b, $c, $dst", []>;
+                   "subcc $b, $c, $dst",
+                   [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
 def SUBCCri : F3_2<2, 0b010100,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "subcc $b, $c, $dst", []>;
+                   "subcc $b, $c, $dst",
+                   [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
 def SUBXCCrr: F3_1<2, 0b011100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "subxcc $b, $c, $dst", []>;