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authorChris Lattner <sabre@nondot.org>2002-10-28 04:30:20 +0000
committerChris Lattner <sabre@nondot.org>2002-10-28 04:30:20 +0000
commit411837979a938de91c1549efd4c185435002317b (patch)
tree0818dfa4ce8b9cd430777a3561b1b2aed2f6b56c /llvm
parent340bb96e642f1dfd1ed64cc87ea1a36d230e9c3c (diff)
downloadbcm5719-llvm-411837979a938de91c1549efd4c185435002317b.tar.gz
bcm5719-llvm-411837979a938de91c1549efd4c185435002317b.zip
Add new getOperandType(i) method to MachineInstr
llvm-svn: 4330
Diffstat (limited to 'llvm')
-rw-r--r--llvm/include/llvm/CodeGen/MachineInstr.h28
1 files changed, 16 insertions, 12 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 0b5ceaf272c..ba901a8d743 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -238,14 +238,6 @@ public:
//
unsigned getNumOperands() const { return operands.size(); }
- bool operandIsDefined(unsigned i) const {
- return getOperand(i).opIsDef();
- }
-
- bool operandIsDefinedAndUsed(unsigned i) const {
- return getOperand(i).opIsDefAndUse();
- }
-
const MachineOperand& getOperand(unsigned i) const {
assert(i < operands.size() && "getOperand() out of range!");
return operands[i];
@@ -254,6 +246,18 @@ public:
assert(i < operands.size() && "getOperand() out of range!");
return operands[i];
}
+
+ MachineOperand::MachineOperandType getOperandType(unsigned i) const {
+ return getOperand(i).getOperandType();
+ }
+
+ bool operandIsDefined(unsigned i) const {
+ return getOperand(i).opIsDef();
+ }
+
+ bool operandIsDefinedAndUsed(unsigned i) const {
+ return getOperand(i).opIsDefAndUse();
+ }
//
// Information about implicit operands of the instruction
@@ -339,7 +343,7 @@ public:
// physical register after register allocation is complete.
//
void SetRegForOperand(unsigned i, int regNum);
-
+
//
// Iterator to enumerate machine operands.
//
@@ -348,10 +352,10 @@ public:
unsigned i;
MITy MI;
- inline void skipToNextVal() {
+ void skipToNextVal() {
while (i < MI->getNumOperands() &&
- !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
- MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
+ !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
+ MI->getOperandType(i) == MachineOperand::MO_CCRegister)
&& MI->getOperand(i).getVRegValue() != 0))
++i;
}
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