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authorSanjay Patel <spatel@rotateright.com>2015-01-28 19:44:21 +0000
committerSanjay Patel <spatel@rotateright.com>2015-01-28 19:44:21 +0000
commit4058dd9f3f17bb91e96bda91ed5ecad183a30cb2 (patch)
tree75f60deaf66e5d6535394828e1e579ab831bf7e1 /llvm
parentd2ef30feed5a6378959770eaed19e9e1b0a1f1c0 (diff)
downloadbcm5719-llvm-4058dd9f3f17bb91e96bda91ed5ecad183a30cb2.tar.gz
bcm5719-llvm-4058dd9f3f17bb91e96bda91ed5ecad183a30cb2.zip
invert check for less indentation; use local vars to reduce duplication; NFC
llvm-svn: 227355
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp39
1 files changed, 20 insertions, 19 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1fd12142966..309080c6982 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -13197,27 +13197,28 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
// the upper bits of a vector.
static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
SelectionDAG &DAG) {
- if (Subtarget->hasFp256()) {
- SDLoc dl(Op);
- SDValue Vec = Op.getOperand(0);
- SDValue SubVec = Op.getOperand(1);
- SDValue Idx = Op.getOperand(2);
-
- if ((Op.getSimpleValueType().is256BitVector() ||
- Op.getSimpleValueType().is512BitVector()) &&
- SubVec.getSimpleValueType().is128BitVector() &&
- isa<ConstantSDNode>(Idx)) {
- unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
- return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
- }
+ if (!Subtarget->hasAVX())
+ return SDValue();
+
+ SDLoc dl(Op);
+ SDValue Vec = Op.getOperand(0);
+ SDValue SubVec = Op.getOperand(1);
+ SDValue Idx = Op.getOperand(2);
+ MVT OpVT = Op.getSimpleValueType();
+ MVT SubVecVT = SubVec.getSimpleValueType();
+
+ if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
+ SubVecVT.is128BitVector() && isa<ConstantSDNode>(Idx)) {
+ unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+ return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
+ }
- if (Op.getSimpleValueType().is512BitVector() &&
- SubVec.getSimpleValueType().is256BitVector() &&
- isa<ConstantSDNode>(Idx)) {
- unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
- return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
- }
+ if (OpVT.is512BitVector() &&
+ SubVecVT.is256BitVector() && isa<ConstantSDNode>(Idx)) {
+ unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+ return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
}
+
return SDValue();
}
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