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authorCraig Topper <craig.topper@intel.com>2019-10-24 17:41:05 -0700
committerCraig Topper <craig.topper@intel.com>2019-10-25 11:11:32 -0700
commit3dd0a896b6402c1abf5cb153a7769cb1bb52bb6e (patch)
treecdf7003a2bef2fff6a861058d37f104be62c79d7 /llvm
parente6c145e0548e3b3de6eab27e44e1504387cf6b53 (diff)
downloadbcm5719-llvm-3dd0a896b6402c1abf5cb153a7769cb1bb52bb6e.tar.gz
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[X86] Add a check for SSE2 to the top of combineReductionToHorizontal.
Without this, we can create a PSADBW node that isn't legal.
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9e628584571..6fb870afdaa 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36266,6 +36266,10 @@ static SDValue combineReductionToHorizontal(SDNode *ExtElt, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
assert(ExtElt->getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unexpected caller");
+ // We need at least SSE2 to anything here.
+ if (!Subtarget.hasSSE2())
+ return SDValue();
+
ISD::NodeType Opc;
SDValue Rdx =
DAG.matchBinOpReduction(ExtElt, Opc, {ISD::ADD, ISD::FADD}, true);
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