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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-12-22 21:48:20 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-12-22 21:48:20 +0000 |
| commit | 3db4952357b70469930d1463a99a17894074784c (patch) | |
| tree | d4e08f11a81e123943d475d5e91ee426b50981eb /llvm | |
| parent | 0a70c4d9a2e5f3a43a539c724923445bcd766627 (diff) | |
| download | bcm5719-llvm-3db4952357b70469930d1463a99a17894074784c.tar.gz bcm5719-llvm-3db4952357b70469930d1463a99a17894074784c.zip | |
Allow explicit %reg0 operands beyond what the .td file describes.
ARM uses these to indicate predicates.
llvm-svn: 91922
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 917d0535b2b..959269f85f2 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -553,7 +553,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { report("Explicit operand marked as implicit", MO, MONum); } } else { - if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) + // ARM adds %reg0 operands to indicate predicates. We'll allow that. + if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) report("Extra explicit operand on non-variadic instruction", MO, MONum); } |
