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authorDmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>2017-04-05 17:26:45 +0000
committerDmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>2017-04-05 17:26:45 +0000
commit3ac6311a8d5d602c4410d956320d522bde27b679 (patch)
treebc56ef1972ef74fc8b1dba74b5ce47d11f6adf4b /llvm
parent3082b8e062ebc77b9b65ae1de3db4918126cd9b4 (diff)
downloadbcm5719-llvm-3ac6311a8d5d602c4410d956320d522bde27b679.tar.gz
bcm5719-llvm-3ac6311a8d5d602c4410d956320d522bde27b679.zip
[AMDGPU][MC] Fix for Bug 28158 + LIT tests
Added support of the following instructions: - s_cbranch_cdbgsys - s_cbranch_cdbgsys_and_user - s_cbranch_cdbgsys_or_user - s_cbranch_cdbguser - s_setkill Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31469 llvm-svn: 299567
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/AMDGPU/SOPInstructions.td20
-rw-r--r--llvm/test/MC/AMDGPU/sopp.s15
2 files changed, 35 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index e6499b9f7b4..3016845c6c3 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -797,6 +797,25 @@ def S_CBRANCH_EXECNZ : SOPP <
>;
} // End Uses = [EXEC]
+def S_CBRANCH_CDBGSYS : SOPP <
+ 0x00000017, (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbgsys $simm16"
+>;
+
+def S_CBRANCH_CDBGSYS_AND_USER : SOPP <
+ 0x0000001A, (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbgsys_and_user $simm16"
+>;
+
+def S_CBRANCH_CDBGSYS_OR_USER : SOPP <
+ 0x00000019, (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbgsys_or_user $simm16"
+>;
+
+def S_CBRANCH_CDBGUSER : SOPP <
+ 0x00000018, (ins sopp_brtarget:$simm16),
+ "s_cbranch_cdbguser $simm16"
+>;
} // End isBranch = 1
} // End isTerminator = 1
@@ -814,6 +833,7 @@ def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
+def S_SETKILL : SOPP <0x0000000b, (ins i16imm:$simm16), "s_setkill $simm16">;
// On SI the documentation says sleep for approximately 64 * low 2
// bits, consistent with the reported maximum of 448. On VI the
diff --git a/llvm/test/MC/AMDGPU/sopp.s b/llvm/test/MC/AMDGPU/sopp.s
index b073c8dfc63..86831f2b75e 100644
--- a/llvm/test/MC/AMDGPU/sopp.s
+++ b/llvm/test/MC/AMDGPU/sopp.s
@@ -43,6 +43,18 @@ s_cbranch_execz 7
s_cbranch_execnz 8
// GCN: s_cbranch_execnz 8 ; encoding: [0x08,0x00,0x89,0xbf]
+s_cbranch_cdbgsys 9
+// GCN: s_cbranch_cdbgsys 9 ; encoding: [0x09,0x00,0x97,0xbf]
+
+s_cbranch_cdbgsys_and_user 10
+// GCN: s_cbranch_cdbgsys_and_user 10 ; encoding: [0x0a,0x00,0x9a,0xbf]
+
+s_cbranch_cdbgsys_or_user 11
+// GCN: s_cbranch_cdbgsys_or_user 11 ; encoding: [0x0b,0x00,0x99,0xbf]
+
+s_cbranch_cdbguser 12
+// GCN: s_cbranch_cdbguser 12 ; encoding: [0x0c,0x00,0x98,0xbf]
+
s_barrier
// GCN: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
@@ -84,6 +96,9 @@ s_waitcnt vmcnt(0), expcnt(0)
s_sethalt 9
// GCN: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]
+s_setkill 7
+// GCN: s_setkill 7 ; encoding: [0x07,0x00,0x8b,0xbf]
+
s_sleep 10
// GCN: s_sleep 10 ; encoding: [0x0a,0x00,0x8e,0xbf]
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