diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-28 15:32:19 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-28 15:32:19 +0000 |
| commit | 39d7720354b17bf10c64f5b585d09bc207227142 (patch) | |
| tree | f68cd6fc63ecb3292266e4a5a9b87bd3f094ef50 /llvm | |
| parent | 318e9d39abf52c347e6a7c7da6ae06399ce6cfa3 (diff) | |
| download | bcm5719-llvm-39d7720354b17bf10c64f5b585d09bc207227142.tar.gz bcm5719-llvm-39d7720354b17bf10c64f5b585d09bc207227142.zip | |
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
llvm-svn: 331110
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 8 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 3 |
4 files changed, 3 insertions, 24 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 8dc684f5591..3066dbb22c3 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -754,13 +754,7 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8", "BTR(16|32|64)ri8", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", - "BTS(16|32|64)rr", - "SAR(8|16|32|64)r1", - "SAR(8|16|32|64)ri", - "SHL(8|16|32|64)r1", - "SHL(8|16|32|64)ri", - "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri")>; + "BTS(16|32|64)rr")>; def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 1081614f7a7..c52d147655d 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -497,15 +497,9 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "SAR(8|16|32|64)r1", - "SAR(8|16|32|64)ri", "SBB(16|32|64)ri", "SBB(16|32|64)i", - "SBB(8|16|32|64)rr", - "SHL(8|16|32|64)r1", - "SHL(8|16|32|64)ri", - "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri")>; + "SBB(8|16|32|64)rr")>; def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 42b93bfffea..22f038292d7 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -802,15 +802,9 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "SAR(8|16|32|64)r1", - "SAR(8|16|32|64)ri", "SBB(16|32|64)ri", "SBB(16|32|64)i", - "SBB(8|16|32|64)rr", - "SHL(8|16|32|64)r1", - "SHL(8|16|32|64)ri", - "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri")>; + "SBB(8|16|32|64)rr")>; def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 85ef171aaea..209fba85148 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -622,9 +622,6 @@ def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>; def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>; // SHRD SHLD. -// r,r -def : InstRW<[WriteShift], (instregex "SH(R|L)D(16|32|64)rri8")>; - // m,r def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>; |
