diff options
| author | Joey Gouly <joey.gouly@arm.com> | 2013-09-18 09:46:49 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-09-18 09:46:49 +0000 |
| commit | 36b2e5de3c3333507dd6d0cd4684859ce0cc010a (patch) | |
| tree | e12a61d55253fe0952aa97140b0d9de3c5c746b8 /llvm | |
| parent | 2f8890ed1ca114aaebb2c8829cbd83eb8d0db194 (diff) | |
| download | bcm5719-llvm-36b2e5de3c3333507dd6d0cd4684859ce0cc010a.tar.gz bcm5719-llvm-36b2e5de3c3333507dd6d0cd4684859ce0cc010a.zip | |
'svn add' the test cases.
llvm-svn: 190929
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/MC/ARM/crc32-thumb.s | 23 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/crc32.s | 23 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/invalid-crc32.s | 16 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/crc32-thumb.txt | 15 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/crc32.txt | 15 |
5 files changed, 92 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/crc32-thumb.s b/llvm/test/MC/ARM/crc32-thumb.s new file mode 100644 index 00000000000..e0f39c31c91 --- /dev/null +++ b/llvm/test/MC/ARM/crc32-thumb.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 + crc32b r0, r1, r2 + crc32h r0, r1, r2 + crc32w r0, r1, r2 + +@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0] +@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0] +@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 + + crc32cb r0, r1, r2 + crc32ch r0, r1, r2 + crc32cw r0, r1, r2 + +@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0] +@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0] +@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 diff --git a/llvm/test/MC/ARM/crc32.s b/llvm/test/MC/ARM/crc32.s new file mode 100644 index 00000000000..eeb6fe89394 --- /dev/null +++ b/llvm/test/MC/ARM/crc32.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 + crc32b r0, r1, r2 + crc32h r0, r1, r2 + crc32w r0, r1, r2 + +@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1] +@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1] +@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 + + crc32cb r0, r1, r2 + crc32ch r0, r1, r2 + crc32cw r0, r1, r2 + +@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1] +@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1] +@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1] +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 diff --git a/llvm/test/MC/ARM/invalid-crc32.s b/llvm/test/MC/ARM/invalid-crc32.s new file mode 100644 index 00000000000..a541002acb1 --- /dev/null +++ b/llvm/test/MC/ARM/invalid-crc32.s @@ -0,0 +1,16 @@ +@ RUN: not llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s + + crc32cbeq r0, r1, r2 + crc32bne r0, r1, r2 + crc32chcc r0, r1, r2 + crc32hpl r0, r1, r2 + crc32cwgt r0, r1, r2 + crc32wle r0, r1, r2 + +@ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified +@ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified diff --git a/llvm/test/MC/Disassembler/ARM/crc32-thumb.txt b/llvm/test/MC/Disassembler/ARM/crc32-thumb.txt new file mode 100644 index 00000000000..2f83b58fd48 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/crc32-thumb.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s + +# CHECK: crc32b r0, r1, r2 +# CHECK: crc32h r0, r1, r2 +# CHECK: crc32w r0, r1, r2 +# CHECK: crc32cb r0, r1, r2 +# CHECK: crc32ch r0, r1, r2 +# CHECK: crc32cw r0, r1, r2 + +0xc1 0xfa 0x82 0xf0 +0xc1 0xfa 0x92 0xf0 +0xc1 0xfa 0xa2 0xf0 +0xd1 0xfa 0x82 0xf0 +0xd1 0xfa 0x92 0xf0 +0xd1 0xfa 0xa2 0xf0 diff --git a/llvm/test/MC/Disassembler/ARM/crc32.txt b/llvm/test/MC/Disassembler/ARM/crc32.txt new file mode 100644 index 00000000000..17bb03220ef --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/crc32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s + +# CHECK: crc32b r0, r1, r2 +# CHECK: crc32h r0, r1, r2 +# CHECK: crc32w r0, r1, r2 +# CHECK: crc32cb r0, r1, r2 +# CHECK: crc32ch r0, r1, r2 +# CHECK: crc32cw r0, r1, r2 + +0x42 0x00 0x01 0xe1 +0x42 0x00 0x21 0xe1 +0x42 0x00 0x41 0xe1 +0x42 0x02 0x01 0xe1 +0x42 0x02 0x21 0xe1 +0x42 0x02 0x41 0xe1 |
