MFTB on PPC64 should really be encoded using MFSPR.

The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.

Thanks to Adhemerval Zanella for pointing this out!

llvm-svn: 161346

2 files changed, 3 insertions, 3 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 92a50516546..5df735aaba7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -266,8 +266,8 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
 }
 
 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
-def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
-                          "mftb $rT", SprMFTB>,
+def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
+                          "mfspr $rT, 268", SprMFTB>,
             PPC970_DGroup_First, PPC970_Unit_FXU;
 
 let Defs = [X1], Uses = [X1] in
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll b/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
index c1df3c7ec21..38406cabb2d 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
@@ -9,7 +9,7 @@ entry:
 }
 
 ; CHECK: @test1
-; CHECK: mftb
+; CHECK: mfspr 3, 268
 
 declare i64 @llvm.readcyclecounter()