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authorDiana Picus <diana.picus@linaro.org>2017-10-06 14:30:05 +0000
committerDiana Picus <diana.picus@linaro.org>2017-10-06 14:30:05 +0000
commit2c9573045059f9c8f33e4d3e1d0850b29b14bd5d (patch)
treedbe9996197275dc4a0b0f1a5192deeb0d5b67afc /llvm
parentc63ed222b8b2dd9ad83005b8378c184840b052d8 (diff)
downloadbcm5719-llvm-2c9573045059f9c8f33e4d3e1d0850b29b14bd5d.tar.gz
bcm5719-llvm-2c9573045059f9c8f33e4d3e1d0850b29b14bd5d.zip
[ARM] GlobalISel: Mark shifts as legal for s32
The new legalize combiner introduces shifts all over the place, so we should support them sooner rather than later. llvm-svn: 315064
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMLegalizerInfo.cpp3
-rw-r--r--llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir79
2 files changed, 82 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 8185f8acc92..695e0f6326d 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -80,6 +80,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setAction({Op, 1, Ty}, Legal);
}
+ for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
+ setAction({Op, s32}, Legal);
+
setAction({G_GEP, p0}, Legal);
setAction({G_GEP, 1, s32}, Legal);
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 1fb7c79cd24..9e7fcc0439a 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -27,6 +27,10 @@
define void @test_xor_s16() { ret void }
define void @test_xor_s32() { ret void }
+ define void @test_lshr_s32() { ret void }
+ define void @test_ashr_s32() { ret void }
+ define void @test_shl_s32() { ret void }
+
define void @test_load_from_stack() { ret void }
define void @test_legal_loads() #0 { ret void }
define void @test_legal_stores() #0 { ret void }
@@ -565,6 +569,81 @@ body: |
...
---
+name: test_lshr_s32
+# CHECK-LABEL: name: test_lshr_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = G_LSHR %0, %1
+ ; G_LSHR with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+
+...
+---
+name: test_ashr_s32
+# CHECK-LABEL: name: test_ashr_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = G_ASHR %0, %1
+ ; G_ASHR with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+
+...
+---
+name: test_shl_s32
+# CHECK-LABEL: name: test_shl_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = G_SHL %0, %1
+ ; G_SHL with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+
+...
+---
name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack
legalized: false
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