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authorElena Demikhovsky <elena.demikhovsky@intel.com>2016-03-29 06:55:56 +0000
committerElena Demikhovsky <elena.demikhovsky@intel.com>2016-03-29 06:55:56 +0000
commit2c35e20dd7f2874314a8f59cd7865a67fb5d1e2c (patch)
tree78cc7cb713ac943caa62c48a19ae75a472d9a87f /llvm
parent0053eb94798e4d9727bb0a52a1f2973572b44f74 (diff)
downloadbcm5719-llvm-2c35e20dd7f2874314a8f59cd7865a67fb5d1e2c.tar.gz
bcm5719-llvm-2c35e20dd7f2874314a8f59cd7865a67fb5d1e2c.zip
Added 2 notes
1) Skylake and KNL support for X86 2) masked intrinsics load/store/gather/scatter Differential Revision: http://reviews.llvm.org/D18353 llvm-svn: 264703
Diffstat (limited to 'llvm')
-rw-r--r--llvm/docs/ReleaseNotes.rst17
1 files changed, 15 insertions, 2 deletions
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 982ade993b3..14fc126ce56 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -71,6 +71,13 @@ Non-comprehensive list of changes in this release
Makes programs 10x faster by doing Special New Thing.
+Changes to the LLVM IR
+----------------------
+
+* New intrinsics ``llvm.masked.load``, ``llvm.masked.store``,
+ ``llvm.masked.gather`` and ``llvm.masked.scatter`` were introduced to the
+ LLVM IR to allow selective memory access for vector data types.
+
Changes to the ARM Backend
--------------------------
@@ -90,9 +97,15 @@ Changes to the PowerPC Target
Changes to the X86 Target
------------------------------
+-------------------------
- During this release ...
+* LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512
+ extensions using ``-march=skylake-avx512``. The switch enables the
+ ISA extensions AVX-512{F, CD, VL, BW, DQ}.
+
+* LLVM now supports the Intel CPU codenamed Knights Landing with AVX-512
+ extensions using ``-march=knl``. The switch enables the ISA extensions
+ AVX-512{F, CD, ER, PF}.
Changes to the AMDGPU Target
-----------------------------
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