[ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32

Mark conversions between pointers and 32-bit scalars as legal, map them
to the GPR and select to a simple COPY.

llvm-svn: 321356

6 files changed, 169 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 2e8e7a7d967..b0fd0b47692 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -788,6 +788,28 @@ bool ARMInstructionSelector::select(MachineInstr &I,
     I.setDesc(TII.get(COPY));
     return selectCopy(I, TII, MRI, TRI, RBI);
   }
+  case G_INTTOPTR:
+  case G_PTRTOINT: {
+    auto SrcReg = I.getOperand(1).getReg();
+    auto DstReg = I.getOperand(0).getReg();
+
+    const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
+    const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
+
+    if (SrcRegBank.getID() != DstRegBank.getID()) {
+      DEBUG(dbgs()
+            << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
+      return false;
+    }
+
+    if (SrcRegBank.getID() != ARM::GPRRegBankID) {
+      DEBUG(dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
+      return false;
+    }
+
+    I.setDesc(TII.get(COPY));
+    return selectCopy(I, TII, MRI, TRI, RBI);
+  }
   case G_SELECT:
     return selectSelect(MIB, MRI);
   case G_ICMP: {
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index d2095587a8b..8cff1f0869d 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -126,6 +126,12 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
     setAction({Op, s32}, Legal);
   }
 
+  setAction({G_INTTOPTR, p0}, Legal);
+  setAction({G_INTTOPTR, 1, s32}, Legal);
+
+  setAction({G_PTRTOINT, s32}, Legal);
+  setAction({G_PTRTOINT, 1, p0}, Legal);
+
   for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
     setAction({Op, s32}, Legal);
 
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 32d1d57d326..fad0e98285e 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -227,6 +227,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case G_ZEXT:
   case G_ANYEXT:
   case G_GEP:
+  case G_INTTOPTR:
+  case G_PTRTOINT:
     // FIXME: We're abusing the fact that everything lives in a GPR for now; in
     // the real world we would use different mappings.
     OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 6ada5b627f0..8b9b83f6d0e 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -49,6 +49,9 @@
   define void @test_constant_cimm() { ret void }
   define void @test_pointer_constant() { ret void }
 
+  define void @test_inttoptr_s32() { ret void }
+  define void @test_ptrtoint_s32() { ret void }
+
   define void @test_select_s32() { ret void }
   define void @test_select_ptr() { ret void }
 
@@ -1124,6 +1127,54 @@ body:             |
     BX_RET 14, %noreg, implicit %r0
 ...
 ---
+name:            test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s32) = COPY %r0
+    %1(p0) = G_INTTOPTR %0(s32)
+    ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY [[INT]]
+
+    %r0 = COPY %1(p0)
+    ; CHECK: %r0 = COPY [[PTR]]
+
+    BX_RET 14, %noreg, implicit %r0
+...
+---
+name:            test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(p0) = COPY %r0
+    %1(s32) = G_PTRTOINT %0(p0)
+    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[INT:%[0-9]+]]:gpr = COPY [[PTR]]
+
+    %r0 = COPY %1(s32)
+    ; CHECK: %r0 = COPY [[INT]]
+
+    BX_RET 14, %noreg, implicit %r0
+...
+---
 name:            test_select_s32
 # CHECK-LABEL: name: test_select_s32
 legalized:       true
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 5725ee7d3c3..204434e981b 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -3,6 +3,9 @@
   define void @test_sext_s8() { ret void }
   define void @test_zext_s16() { ret void }
 
+  define void @test_inttoptr_s32() { ret void }
+  define void @test_ptrtoint_s32() { ret void }
+
   define void @test_add_s8() { ret void }
   define void @test_add_s16() { ret void }
   define void @test_add_s32() { ret void }
@@ -101,6 +104,50 @@ body:             |
     BX_RET 14, %noreg, implicit %r0
 ...
 ---
+name:            test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s32) = COPY %r0
+    %1(p0) = G_INTTOPTR %0(s32)
+    ; G_INTTOPTR with s32 is legal, so we should find it unchanged in the output
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_INTTOPTR {{%[0-9]+}}
+    %r0 = COPY %1(p0)
+    BX_RET 14, %noreg, implicit %r0
+...
+---
+name:            test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(p0) = COPY %r0
+    %1(s32) = G_PTRTOINT %0(p0)
+    ; G_PTRTOINT with s32 is legal, so we should find it unchanged in the output
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_PTRTOINT {{%[0-9]+}}
+    %r0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %r0
+...
+---
 name:            test_add_s8
 # CHECK-LABEL: name: test_add_s8
 legalized:       false
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index 1ce4b8b98ec..175333626f9 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -24,6 +24,9 @@
 
   define void @test_constants() { ret void }
 
+  define void @test_inttoptr_s32() { ret void }
+  define void @test_ptrtoint_s32() { ret void }
+
   @a_global = global float 1.0
   define void @test_globals() { ret void }
 
@@ -497,6 +500,44 @@ body:             |
     BX_RET 14, %noreg, implicit %r0
 ...
 ---
+name:            test_inttoptr_s32
+# CHECK-LABEL: name: test_inttoptr_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    %0(s32) = COPY %r0
+    %1(p0) = G_INTTOPTR %0(s32)
+    %r0 = COPY %1(p0)
+    BX_RET 14, %noreg, implicit %r0
+...
+---
+name:            test_ptrtoint_s32
+# CHECK-LABEL: name: test_ptrtoint_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: gprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    %0(p0) = COPY %r0
+    %1(s32) = G_PTRTOINT %0(p0)
+    %r0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %r0
+...
+---
 name:            test_globals
 # CHECK-LABEL: name: test_globals
 legalized:       true