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| author | Dan Gohman <gohman@apple.com> | 2008-08-20 18:10:48 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-20 18:10:48 +0000 |
| commit | 24e8f0cfe6f47ddef28bcef75c92f000272fe661 (patch) | |
| tree | e3dd698a62ee63504f1f7a3144e7d6775d94fd58 /llvm | |
| parent | 2471f6ce0f74244ce5307428be0f9e9b5fede912 (diff) | |
| download | bcm5719-llvm-24e8f0cfe6f47ddef28bcef75c92f000272fe661.tar.gz bcm5719-llvm-24e8f0cfe6f47ddef28bcef75c92f000272fe661.zip | |
Minor code reorganization.
llvm-svn: 55071
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 7cb888ccb98..954de1d059a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -146,8 +146,8 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType, unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) { MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetInstrDesc &II = TII->get(MachineInstOpcode); unsigned ResultReg = MRI.createVirtualRegister(RC); + const TargetInstrDesc &II = TII->get(MachineInstOpcode); MachineInstr *MI = BuildMI(*MF, II, ResultReg); @@ -159,8 +159,8 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0) { MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetInstrDesc &II = TII->get(MachineInstOpcode); unsigned ResultReg = MRI.createVirtualRegister(RC); + const TargetInstrDesc &II = TII->get(MachineInstOpcode); MachineInstr *MI = BuildMI(*MF, II, ResultReg); MI->addOperand(MachineOperand::CreateReg(Op0, false)); @@ -173,8 +173,8 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) { MachineRegisterInfo &MRI = MF->getRegInfo(); - const TargetInstrDesc &II = TII->get(MachineInstOpcode); unsigned ResultReg = MRI.createVirtualRegister(RC); + const TargetInstrDesc &II = TII->get(MachineInstOpcode); MachineInstr *MI = BuildMI(*MF, II, ResultReg); MI->addOperand(MachineOperand::CreateReg(Op0, false)); |
