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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-05-16 16:15:18 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-05-16 16:15:18 +0000 |
| commit | 22f9191979f02e7930b83e4b55b8a70456c55fa9 (patch) | |
| tree | 13c03b9db6e6df0e29fb5d9149ed01f3c751a6c6 /llvm | |
| parent | 12adfd8e231cf75bb8d4a6e19bcb18220d5c0c72 (diff) | |
| download | bcm5719-llvm-22f9191979f02e7930b83e4b55b8a70456c55fa9.tar.gz bcm5719-llvm-22f9191979f02e7930b83e4b55b8a70456c55fa9.zip | |
Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll
While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler. The new CHECK-DAG support is perfect for
avoiding this problem.
llvm-svn: 182020
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/recipest.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll index 89705faa46e..38d76820bb7 100644 --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -14,8 +14,8 @@ entry: ret double %r ; CHECK: @foo -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -39,8 +39,8 @@ entry: ret double %r ; CHECK: @foof -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -61,8 +61,8 @@ entry: ret float %r ; CHECK: @foo -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -86,8 +86,8 @@ entry: ret float %r ; CHECK: @goo -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -120,8 +120,8 @@ entry: ret double %r ; CHECK: @foo2 -; CHECK: fre -; CHECK: fnmsub +; CHECK-DAG: fre +; CHECK-DAG: fnmsub ; CHECK: fmadd ; CHECK: fnmsub ; CHECK: fmadd @@ -139,8 +139,8 @@ entry: ret float %r ; CHECK: @goo2 -; CHECK: fres -; CHECK: fnmsubs +; CHECK-DAG: fres +; CHECK-DAG: fnmsubs ; CHECK: fmadds ; CHECK: fmuls ; CHECK: blr @@ -169,8 +169,8 @@ entry: ret double %r ; CHECK: @foo3 -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -195,8 +195,8 @@ entry: ret float %r ; CHECK: @goo3 -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls |
